Struct lpc845_pac::adc0::ctrl::CLKDIV_R

pub struct CLKDIV_R(_);

Field CLKDIV reader - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.

Methods from Deref<Target = FieldReader<u8, u8>>

pub fn bits(&self) -> U

Reads raw bits from field.

pub fn bit(&self) -> bool

Value of the field as raw bits.

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0).

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1).

Trait Implementations

impl Deref for CLKDIV_R

type Target = FieldReader<u8, u8>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.