Enum lpc845_pac::adc0::ctrl::LPWRMODE_A[][src]

pub enum LPWRMODE_A {
    LPWRMODE_0,
    LPWRMODE_1,
}
Expand description

The low-power ADC mode

Value on reset: 0

Variants

LPWRMODE_0

0: The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.

LPWRMODE_1

1: The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low.

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