Struct lpc82x::sct::ctrl::W
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pub struct W { /* fields omitted */ }
Value to write to the register
Methods
impl W
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fn reset_value() -> W
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Reset value of the register
unsafe fn bits(&mut self, bits: u32) -> &mut Self
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Writes raw bits to the register
fn down_l(&mut self) -> _DOWN_LW
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Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
fn stop_l(&mut self) -> _STOP_LW
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Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
fn halt_l(&mut self) -> _HALT_LW
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Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.
fn clrctr_l(&mut self) -> _CLRCTR_LW
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Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
fn bidir_l(&mut self) -> _BIDIR_LW
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Bit 4 - L or unified counter direction select
fn pre_l(&mut self) -> _PRE_LW
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Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
fn down_h(&mut self) -> _DOWN_HW
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Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
fn stop_h(&mut self) -> _STOP_HW
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Bit 17 - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
fn halt_h(&mut self) -> _HALT_HW
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Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.
fn clrctr_h(&mut self) -> _CLRCTR_HW
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Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
fn bidir_h(&mut self) -> _BIDIR_HW
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Bit 20 - Direction select
fn pre_h(&mut self) -> _PRE_HW
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Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.