Module lpc82x_pac::adc0::flags [−][src]
Expand description
ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
Structs
ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
Field OVERRUN0 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
Field OVERRUN1 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
Field OVERRUN2 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
Field OVERRUN3 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
Field OVERRUN4 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
Field OVERRUN5 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
Field OVERRUN6 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
Field OVERRUN7 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
Field OVERRUN8 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
Field OVERRUN9 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
Field OVERRUN10 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
Field OVERRUN11 reader - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
Field OVR_INT reader - Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.
Register FLAGS reader
Field SEQA_INT reader - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.
Field SEQA_OVR reader - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
Field SEQB_INT reader - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.
Field SEQB_OVR reader - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
Field THCMP0 reader - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.
Field THCMP0 writer - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.
Field THCMP1 reader - Threshold comparison event on Channel 1. See description for channel 0.
Field THCMP1 writer - Threshold comparison event on Channel 1. See description for channel 0.
Field THCMP2 reader - Threshold comparison event on Channel 2. See description for channel 0.
Field THCMP2 writer - Threshold comparison event on Channel 2. See description for channel 0.
Field THCMP3 reader - Threshold comparison event on Channel 3. See description for channel 0.
Field THCMP3 writer - Threshold comparison event on Channel 3. See description for channel 0.
Field THCMP4 reader - Threshold comparison event on Channel 4. See description for channel 0.
Field THCMP4 writer - Threshold comparison event on Channel 4. See description for channel 0.
Field THCMP5 reader - Threshold comparison event on Channel 5. See description for channel 0.
Field THCMP5 writer - Threshold comparison event on Channel 5. See description for channel 0.
Field THCMP6 reader - Threshold comparison event on Channel 6. See description for channel 0.
Field THCMP6 writer - Threshold comparison event on Channel 6. See description for channel 0.
Field THCMP7 reader - Threshold comparison event on Channel 7. See description for channel 0.
Field THCMP7 writer - Threshold comparison event on Channel 7. See description for channel 0.
Field THCMP8 reader - Threshold comparison event on Channel 8. See description for channel 0.
Field THCMP8 writer - Threshold comparison event on Channel 8. See description for channel 0.
Field THCMP9 reader - Threshold comparison event on Channel 9. See description for channel 0.
Field THCMP9 writer - Threshold comparison event on Channel 9. See description for channel 0.
Field THCMP10 reader - Threshold comparison event on Channel 10. See description for channel 0.
Field THCMP10 writer - Threshold comparison event on Channel 10. See description for channel 0.
Field THCMP11 reader - Threshold comparison event on Channel 11. See description for channel 0.
Field THCMP11 writer - Threshold comparison event on Channel 11. See description for channel 0.
Field THCMP_INT reader - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.
Register FLAGS writer