Type Definition lpc82x_pac::adc0::ctrl::W

type W = W<u32, CTRL>;

Writer for register CTRL

Methods

impl W

pub fn clkdiv(&mut self) -> CLKDIV_W

Bits 0:7 - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.

pub fn lpwrmode(&mut self) -> LPWRMODE_W

Bit 10 - The low-power ADC mode

pub fn calmode(&mut self) -> CALMODE_W

Bit 30 - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended.