lpc81x-hal 0.1.0

<?xml version="1.0" encoding="utf-8"?> 

<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
	<name>LPC800</name>
	<version>0.2</version>
	<description>LPC800</description>
	<!-- this is really a M0+ core -->
	<cpu>
		<name>CM0</name>
		<revision>r0p0</revision>
		<endian>little</endian>
		<mpuPresent>0</mpuPresent>
		<fpuPresent>0</fpuPresent>
		<nvicPrioBits>2</nvicPrioBits>
		<vendorSystickConfig>0</vendorSystickConfig>
	</cpu>
	<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
	<addressUnitBits>8</addressUnitBits>
	<width>32</width>
	<size>32</size>

	<!--
		Software that is described herein is for illustrative purposes only
		which provides customers with programming information regarding the
		products. This software is supplied "AS IS" without any warranties.
		NXP Semiconductors assumes no responsibility or liability for the
		use of the software, conveys no license or title under any patent,
		copyright, or mask work right to the product. NXP Semiconductors
		reserves the right to make changes in the software without
		notification. NXP Semiconductors also make no representation or
		warranty that such application will be suitable for the specified
		use without further testing or modification.	
		
	-->	




	

	<peripherals>
		<peripheral>
			<name>WWDT</name>
			<description>Windowed Watchdog Timer (WWDT)</description>
			<groupName>WWDT</groupName>
			<baseAddress>0x40000000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>WDT</name>
				<value>12</value>
			</interrupt>
			<registers>
				<register>
					<name>MOD</name>
					<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
					<addressOffset>0x000</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>WDEN</name>
							<description>Watchdog enable bit. Once this bit has been written with a 1, it cannot be rewritten with a 0.</description>
							<bitRange>[0:0]</bitRange>
							<enumeratedValues>
								<name>ENUM</name>
								<enumeratedValue>
									<name>STOPPED</name>
									<description>The watchdog timer is stopped.</description>
									<value>0</value>
								</enumeratedValue>
								<enumeratedValue>
									<name>RUNNING</name>
									<description>The watchdog timer is running.</description>
									<value>1</value>
								</enumeratedValue>
							</enumeratedValues>
						</field>
						<field>
							<name>WDRESET</name>
							<description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
							<bitRange>[1:1]</bitRange>
							<enumeratedValues>
								<name>ENUM</name>
								<enumeratedValue>
									<name>NORESET</name>
									<description>A watchdog timeout will not cause a chip reset.</description>
									<value>0</value>
								</enumeratedValue>
								<enumeratedValue>
									<name>RESET</name>
									<description>A watchdog timeout will cause a chip reset.</description>
									<value>1</value>
								</enumeratedValue>
							</enumeratedValues>
						</field>
						<field>
							<name>WDTOF</name>
							<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.</description>
							<bitRange>[2:2]</bitRange>
							
						</field>
						<field>
							<name>WDINT</name>
							<description>Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.</description>
							<bitRange>[3:3]</bitRange>
							
						</field>
						<field>
							<name>WDPROTECT</name>
							<description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
							<bitRange>[4:4]</bitRange>
							<enumeratedValues>
								<name>ENUM</name>
								<enumeratedValue>
									<name>PROTECTED</name>
									<description>The watchdog time-out value (TC) can be changed at any time.</description>
									<value>0</value>
								</enumeratedValue>
								<enumeratedValue>
									<name>UNPROTECTED</name>
									<description>The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
									<value>1</value>
								</enumeratedValue>
							</enumeratedValues>
						</field>
						<field>
							<name>LOCK</name>
							<description>A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset.</description>
							<bitRange>[5:5]</bitRange>
							
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
							<bitRange>[31:6]</bitRange>
							
						</field>
					</fields>
				</register>
				<register>
					<name>TC</name>
					<description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
					<addressOffset>0x004</addressOffset>
					<access>read-write</access>
					<resetValue>0xFF</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>COUNT</name>
							<description>Watchdog time-out value.</description>
							<bitRange>[23:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
							<bitRange>[31:24]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>FEED</name>
					<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
					<addressOffset>0x008</addressOffset>
					<access>write-only</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>FEED</name>
							<description>Feed value should be 0xAA followed by 0x55.</description>
							<bitRange>[7:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
							<bitRange>[31:8]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>TV</name>
					<description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
					<addressOffset>0x00C</addressOffset>
					<access>read-only</access>
					<resetValue>0xFF</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>COUNT</name>
							<description>Counter timer value.</description>
							<bitRange>[23:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
							<bitRange>[31:24]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>WARNINT</name>
					<description>Watchdog Warning Interrupt compare value.</description>
					<addressOffset>0x014</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>WARNINT</name>
							<description>Watchdog warning interrupt compare value.</description>
							<bitRange>[9:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
							<bitRange>[31:10]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>WINDOW</name>
					<description>Watchdog Window compare value.</description>
					<addressOffset>0x018</addressOffset>
					<access>read-write</access>
					<resetValue>0xFFFFFF</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>WINDOW</name>
							<description>Watchdog window value.</description>
							<bitRange>[23:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
							<bitRange>[31:24]</bitRange>
						</field>
					</fields>
				</register>
			</registers>
		</peripheral>
		<peripheral>
			<name>MRT</name>
			<description>Multi-Rate Timer (MRT)</description>
			<groupName>MRT</groupName>
			<baseAddress>0x40004000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>MRT</name>
				<value>10</value>
			</interrupt>
		<registers>						
	<register>					
		<dim>4</dim>				
		<dimIncrement>0x10</dimIncrement>				
		<dimIndex>0-3</dimIndex>				
		<name>INTVAL%s</name>				
		<description>MRT0 Time interval value register. This value is loaded into the TIMER0 register.</description>				
		<addressOffset>0x0</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>IVALUE</name>		
				<description>Time interval load value. This value is loaded into the TIMERn register and the MRTn starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately.  If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>		
				<bitRange>[23:0]</bitRange>		
					
			</field>
			<field>
			<name>RESERVED</name>
			<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
			<bitRange>[30:24]</bitRange>	
			</field>
			<field>			
				<name>LOAD</name>		
				<description>Determines how the timer interval value IVALUE is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>		
				<bitRange>[31:31]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_FORCE_LOAD_THE_L</name>
						<description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>FORCE_LOAD_THE_INTV</name>
						<description>Force load. The INTVALn interval value IVALUE is immediately loaded into the TIMERn register while TIMERn is running.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<dim>4</dim>				
		<dimIncrement>0x10</dimIncrement>				
		<dimIndex>0-3</dimIndex>				
		<name>TIMER%s</name>				
		<description>MRT0 Timer register. This register reads the value of the down-counter.</description>				
		<addressOffset>0x4</addressOffset>				
		<access>read-only</access>				
		<resetValue>0x00FFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>VALUE</name>		
				<description>Holds the current timer value of the down-counter. The initial value is loaded as IVALUE - 1 from the TIME_INTVALn register either at the end of the time interval if the LOAD bit in TIME_INTVALn is 0 and the timer is in repeat mode or immediately if LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x7FFF FFFF).</description>		
				<bitRange>[23:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<dim>4</dim>				
		<dimIncrement>0x10</dimIncrement>				
		<dimIndex>0-3</dimIndex>				
		<name>CTRL%s</name>				
		<description>MRT0 Control register. This register controls the MRT0 modes.</description>				
		<addressOffset>0x8</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>INTEN</name>		
				<description>Enable the TIMERn interrupt.</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE_</name>
						<description>Disable.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE_</name>
						<description>Enable.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>MODE</name>		
				<description>Selects timer mode.</description>		
				<bitRange>[2:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>REPEAT_INTERRUPT_MOD</name>
						<description>Repeat interrupt mode.</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ONE_SHOT_INTERRUPT_M</name>
						<description>One-shot interrupt mode.</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ONE_SHOT_BUS_STALL_M</name>
						<description>One-shot bus stall mode.</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RESERVED_</name>
						<description>Reserved.</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:3]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<dim>4</dim>				
		<dimIncrement>0x10</dimIncrement>				
		<dimIndex>0-3</dimIndex>				
		<name>STAT%s</name>				
		<description>MRT0 Status register.</description>				
		<addressOffset>0xC</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>INTFLAG</name>		
				<description>Monitors the interrupt flag.</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_PENDING_INTERRUPT</name>
						<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PENDING_INTERRUPT_T</name>
						<description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised.  Writing a 1 to this bit clears the interrupt request.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RUN</name>		
				<description>Indicates the state of TIMERn. This bit is read-only.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>IDLE_STATE_TIMERN_I</name>
						<description>Idle state. TIMERn is stopped.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RUNNING_TIMERN_IS_R</name>
						<description>Running. TIMERn is running.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:2]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IDLE_CH</name>				
		<description>Idle channel register. This register returns the number of the first idle channel.</description>				
		<addressOffset>0xF4</addressOffset>				
		<access>read-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[3:0]</bitRange>		
			</field>			
			<field>			
				<name>CHAN</name>		
				<description>Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. If all timer channels are running, CHAN = .</description>		
				<bitRange>[7:4]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IRQ_FLAG</name>				
		<description>Global interrupt flag register</description>				
		<addressOffset>0xF8</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>GFLAG0</name>		
				<description>Monitors the interrupt flag of TIMER0.</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_PENDING_INTERRUPT</name>
						<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PENDING_INTERRUPT_T</name>
						<description>Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised.  Writing a 1 to this bit clears the interrupt request.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>GFLAG1</name>		
				<description>Monitors the interrupt flag of TIMER1.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_PENDING_INTERRUPT</name>
						<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PENDING_INTERRUPT_T</name>
						<description>Pending interrupt. The interrupt is pending because TIMER1 has reached the end of the time interval. If the INTEN bit in the CONTROL1 register is also set to 1, the interrupt for timer channel 1 and the global interrupt are raised.  Writing a 1 to this bit clears the interrupt request.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>GFLAG2</name>		
				<description>Monitors the interrupt flag of TIMER2.</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_PENDING_INTERRUPT</name>
						<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PENDING_INTERRUPT_T</name>
						<description>Pending interrupt. The interrupt is pending because TIMER2 has reached the end of the time interval. If the INTEN bit in the CONTROL2 register is also set to 1, the interrupt for timer channel 2 and the global interrupt are raised.  Writing a 1 to this bit clears the interrupt request.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>GFLAG3</name>		
				<description>Monitors the interrupt flag of TIMER3.</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_PENDING_INTERRUPT</name>
						<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PENDING_INTERRUPT_T</name>
						<description>Pending interrupt. The interrupt is pending because TIMER3 has reached the end of the time interval. If the INTEN bit in the CONTROL3 register is also set to 1, the interrupt for timer channel 3 and the global interrupt are raised.  Writing a 1 to this bit clears the interrupt request.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:4]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
</registers>						
							
																										

			
			
		</peripheral>
		<peripheral>
			<name>WKT</name>
			<description>Self wake-up timer (WKT)</description>
			<groupName>WKT</groupName>
			<baseAddress>0x40008000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>WKT</name>
				<value>15</value>
			</interrupt>
			<registers>
				<register>
					<name>CTRL</name>
					<description>Self wake-up timer control register.</description>
					<addressOffset>0x0</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>CLKSEL</name>
							<description>Select the self wake-up timer clock source.</description>
							<bitRange>[0:0]</bitRange>
							<enumeratedValues>
								<name>ENUM</name>
								<enumeratedValue>
									<name>DIVIDED_IRC_CLOCK_T</name>
									<description>Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. This clock is not available in most low-power modes and must not be selected if the timer is to be used to wake up from one of these modes.</description>
									<value>0</value>
								</enumeratedValue>
								<enumeratedValue>
									<name>LOW_POWER_CLOCK_THI</name>
									<description>Low power clock. This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 CTS can be from the input pin, or fs increments. The accuracy of this clock is limited to +/- 45 % over temperature and processing. This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed.</description>
									<value>1</value>
								</enumeratedValue>
							</enumeratedValues>
						</field>
						<field>
							<name>ALARMFLAG</name>
							<description>Wake-up or alarm timer flag.</description>
							<bitRange>[1:1]</bitRange>
							<enumeratedValues>
								<name>ENUM</name>
								<enumeratedValue>
									<name>NO_TIME_OUT_THE_SEL</name>
									<description>No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.</description>
									<value>0</value>
								</enumeratedValue>
								<enumeratedValue>
									<name>TIME_OUT_THE_SELF_W</name>
									<description>Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any low power mode not deep power-down. Writing a 1 clears this status bit and the interrupt too?</description>
									<value>1</value>
								</enumeratedValue>
							</enumeratedValues>
						</field>
						<field>
							<name>CLEARCTR</name>
							<description>Clears the self wake-up timer.</description>
							<bitRange>[2:2]</bitRange>
							<enumeratedValues>
								<name>ENUM</name>
								<enumeratedValue>
									<name>NO_EFFECT_READING_T</name>
									<description>No effect. Reading this bit always returns 0.</description>
									<value>0</value>
								</enumeratedValue>
								<enumeratedValue>
									<name>CLEAR_THE_COUNTER_C</name>
									<description>Clear the counter. Counting is halted until a new count value is loaded.</description>
									<value>1</value>
								</enumeratedValue>
							</enumeratedValues>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:3]</bitRange>
							
						</field>
					</fields>
				</register>
				<register>
					<name>COUNT</name>
					<description>Counter register.</description>
					<addressOffset>0xC</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>VALUE</name>
							<description>A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer.</description>
							<bitRange>[31:0]</bitRange>
						</field>
					</fields>
				</register>
			</registers>
		</peripheral>
		
		
		
		
		<peripheral>
	<name>SWM</name>
	<description>Switch matrix (SWM)</description>
	<groupName>SWM</groupName>
	<baseAddress>0x4000C000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
									
<registers>						
	<register>					
		<name>PINASSIGN0</name>				
		<description>Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS</description>				
		<addressOffset>0x000</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>U0_TXD_O</name>		
				<description>U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>U0_RXD_I</name>		
				<description>U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>U0_RTS_O</name>		
				<description>U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>U0_CTS_I</name>		
				<description>U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN1</name>				
		<description>Pin assign register 1. Assign movable functions U0_SCLC, U1_TXD, U1_RXD</description>				
		<addressOffset>0x004</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>U0_SCLK_IO</name>		
				<description>U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>U1_TXD_O</name>		
				<description>U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>U1_RXD_I</name>		
				<description>U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>U1_RTS_O</name>		
				<description>U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN2</name>				
		<description>Pin assign register 2. Assign movable functions U2_TXD, U2_RXD</description>				
		<addressOffset>0x008</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>U1_CTS_I</name>		
				<description>U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>U1_SCLK_IO</name>		
				<description>U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>U2_TXD_O</name>		
				<description>U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>U2_RXD_I</name>		
				<description>U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN3</name>				
		<description>Pin assignregister 3. Assign movable function SPI0_SCK</description>				
		<addressOffset>0x00C</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>U2_RTS_O</name>		
				<description>U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>U2_CTS_I</name>		
				<description>U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>U2_SCLK_IO</name>		
				<description>U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>SPI0_SCK_IO</name>		
				<description>SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN4</name>				
		<description>Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL, SPI1_SCK</description>				
		<addressOffset>0x010</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SPI0_MOSI_IO</name>		
				<description>SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>SPI0_MISO_IO</name>		
				<description>SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>SPI0_SSEL_IO</name>		
				<description>SPI0_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>SPI1_SCK_IO</name>		
				<description>SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN5</name>				
		<description>Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO, SPI1_SSEL, CTIN_0</description>				
		<addressOffset>0x014</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SPI1_MOSI_IO</name>		
				<description>SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>SPI1_MISO_IO</name>		
				<description>SPI1_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>SPI1_SSEL_IO</name>		
				<description>SPI1_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>CTIN_0_I</name>		
				<description>CTIN_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN6</name>				
		<description>Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3, CTOUT_0</description>				
		<addressOffset>0x018</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>CTIN_1_I</name>		
				<description>CTIN_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>CTIN_2_I</name>		
				<description>CTIN_2function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>CTIN_3_I</name>		
				<description>CTIN_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>CTOUT_0_O</name>		
				<description>CTOUT_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN7</name>				
		<description>Pin assign egister 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3, I2C_SDA</description>				
		<addressOffset>0x01C</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>CTOUT_1_O</name>		
				<description>CTOUT_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>CTOUT_2_O</name>		
				<description>CTOUT_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>CTOUT_3_O</name>		
				<description>CTOUT_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>I2C_SDA_IO</name>		
				<description>I2C_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINASSIGN8</name>				
		<description>Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT, GPIO_INT_BMAT</description>				
		<addressOffset>0x020</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFFFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>I2C_SCL_IO</name>		
				<description>I2C_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>ACMP_O_O</name>		
				<description>ACMP_O_O function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[15:8]</bitRange>		
			</field>			
			<field>			
				<name>CLKOUT_O</name>		
				<description>CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[23:16]</bitRange>		
			</field>			
			<field>			
				<name>GPIO_INT_BMAT_O</name>		
				<description>GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).</description>		
				<bitRange>[31:24]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PINENABLE0</name>				
		<description>Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP</description>				
		<addressOffset>0x1C0</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x1B3</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>ACMP_I1_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_ACMP_I1_THIS</name>
						<description>Enable ACMP_I1. This function is enabled on pin PIO0_0.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_ACMP_I1_GPI</name>
						<description>Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function can be assigned to pin PIO0_0.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>ACMP_I2_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_ACMP_I2_THIS</name>
						<description>Enable ACMP_I2. This function is enabled on pin PIO0_1.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_ACMP_I2_GPI</name>
						<description>Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin PIO0_1.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SWCLK_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_SWCLK_THIS_F</name>
						<description>Enable SWCLK. This function is enabled on pin PIO0_3.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_SWCLK_GPIO_</name>
						<description>Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable function can be assigned to pin PIO0_3.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SWDIO_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_SWDIO_THIS_F</name>
						<description>Enable SWDIO. This function is enabled on pin PIO0_2.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_SWDIO_GPIO_</name>
						<description>Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable function can be assigned to pin PIO0_2.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>XTALIN_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.</description>		
				<bitRange>[4:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_XTALIN_THIS_</name>
						<description>Enable XTALIN. This function is enabled on pin PIO0_8.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_XTALIN_GPIO</name>
						<description>Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function can be assigned to pin PIO0_8.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>XTALOUT_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.</description>		
				<bitRange>[5:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_XTALOUT_THIS</name>
						<description>Enable XTALOUT. This function is enabled on pin PIO0_9.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_XTALOUT_GPI</name>
						<description>Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function can be assigned to pin PIO0_9.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESET_EN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_RESET_THIS_F</name>
						<description>Enable RESET. This function is enabled on pin PIO0_5.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_RESET_GPIO_</name>
						<description>Disable RESET. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>CLKIN</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN.</description>		
				<bitRange>[7:7]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_CLKIN_THIS_F</name>
						<description>Enable CLKIN. This function is enabled on pin PIO0_1.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_CLKIN_GPIO_</name>
						<description>Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin CLKIN.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>VDDCMP</name>		
				<description>Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.</description>		
				<bitRange>[8:8]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLE_VDDCMP_THIS_</name>
						<description>Enable VDDCMP. This function is enabled on pin PIO0_6.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLE_VDDCMP_GPIO</name>
						<description>Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function can be assigned to pin PIO0_6.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:9]</bitRange>		
						
			</field>			
		</fields>				
	</register>					
</registers>						

	
		</peripheral>
		<peripheral>
			<name>PMU</name>
			<description>Power Management Unit (PMU)</description>
			<groupName>PMU</groupName>
			<baseAddress>0x40020000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<registers>						
				<register>					
					<name>PCON</name>				
					<description>Power control register</description>				
					<addressOffset>0x000</addressOffset>				
					<access>read-write</access>				
					<resetValue>0x0</resetValue>				
					<resetMask>0xFFFFFFFF</resetMask>				
					<fields>				
						<field>			
							<name>PM</name>		
							<description>Power mode</description>		
							<bitRange>[2:0]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>DEFAULT_THE_PART_IS</name>
									<description>Default. The part is in active or sleep mode.</description>
									<value>0x0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>ARM_WFI_WILL_ENTER_DEEP_SLEEP</name>
									<description>ARM WFI will enter Deep-sleep mode.</description>
									<value>0x1</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>ARM_WFI_WILL_ENTER_P</name>
									<description>ARM WFI will enter Power-down mode.</description>
									<value>0x2</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>ARM_WFI_WILL_ENTER_DEEP_POWER_DOWN</name>
									<description>ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down).</description>
									<value>0x3</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>NODPD</name>		
							<description>A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed.   This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.</description>		
							<bitRange>[3:3]</bitRange>		
								
						</field>			
						<field>			
							<name>RESERVED</name>		
							<description>Reserved. Do not write ones to this bit.</description>		
							<bitRange>[7:4]</bitRange>		
								
						</field>			
						<field>			
							<name>SLEEPFLAG</name>		
							<description>Sleep mode flag</description>		
							<bitRange>[8:8]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>READ_NO_POWER_DOWN_</name>
									<description>Read: No power-down mode entered. LPC11Uxx is in Active mode. Write: No effect.</description>
									<value>0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>READ_SLEEPDEEP_SLE</name>
									<description>Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
									<value>1</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>RESERVED</name>		
							<description>Reserved. Do not write ones to this bit.</description>		
							<bitRange>[10:9]</bitRange>		
								
						</field>			
						<field>			
							<name>DPDFLAG</name>		
							<description>Deep power-down flag</description>		
							<bitRange>[11:11]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>READ_DEEP_POWER_DOWN_NOT_ENTERED</name>
									<description>Read: Deep power-down mode  not entered. Write: No effect.</description>
									<value>0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>READ_DEEP_POWER_DOWN_ENTERED</name>
									<description>Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
									<value>1</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>RESERVED</name>		
							<description>Reserved. Do not write ones to this bit.</description>		
							<bitRange>[31:12]</bitRange>		
								
						</field>			
					</fields>				
				</register>					
				<register>					
					<dim>4</dim>				
					<dimIncrement>0x4</dimIncrement>				
					<dimIndex>0-3</dimIndex>				
					<name>GPREG%s</name>				
					<description>General purpose register 0</description>				
					<addressOffset>0x004</addressOffset>				
					<access>read-write</access>				
					<resetValue>0x0</resetValue>				
					<resetMask>0xFFFFFFFF</resetMask>				
					<fields>				
						<field>			
							<name>GPDATA</name>		
							<description>Data retained during Deep power-down mode.</description>		
							<bitRange>[31:0]</bitRange>		
						</field>			
					</fields>				
				</register>					
				<register>					
					<name>DPDCTRL</name>				
					<description>Deep power-down control register</description>				
					<addressOffset>0x014</addressOffset>				
					<access>read-write</access>				
					<resetValue>0x0</resetValue>				
					<resetMask>0xFFFFFFFF</resetMask>				
					<fields>				
						<field>			
							<name>WAKEUPHYS</name>		
							<description>WAKEUP pin hysteresis enable</description>		
							<bitRange>[0:0]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>DISABLED_HYSTERESIS</name>
									<description>Disabled. Hysteresis for WAKUP pin disabled.</description>
									<value>0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>ENABLED_HYSTERESIS_</name>
									<description>Enabled. Hysteresis for WAKEUP pin enabled.</description>
									<value>1</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>WAKEPAD_DISABLE</name>		
							<description>WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used.</description>		
							<bitRange>[1:1]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>ENABLED_THE_WAKE_UP</name>
									<description>Enabled. The wake-up function is enabled on pin PIO0_4.</description>
									<value>0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>DISABLED_SETTING_TH</name>
									<description>Disabled. Setting this bit disables the wake-up function on pin PIO0_4.</description>
									<value>1</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>LPOSCEN</name>		
							<description>Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set.  Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC.</description>		
							<bitRange>[2:2]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>DISABLED_</name>
									<description>Disabled.</description>
									<value>0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>ENABLED_</name>
									<description>Enabled.</description>
									<value>1</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>LPOSCDPDEN</name>		
							<description>Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 12 in this register is set as well.  You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Do not set this bit unless you must use the self wake-up timer to wake up from Deep power-down mode.</description>		
							<bitRange>[3:3]</bitRange>		
							<enumeratedValues>		
								<name>ENUM</name>		
								<enumeratedValue>	
									<name>DISABLED_</name>
									<description>Disabled.</description>
									<value>0</value>
								</enumeratedValue>	
								<enumeratedValue>	
									<name>ENABLED_</name>
									<description>Enabled.</description>
									<value>1</value>
								</enumeratedValue>	
							</enumeratedValues>		
						</field>			
						<field>			
							<name>RESERVED</name>		
							<description>Data retained during Deep power-down mode. or reserved?</description>		
							<bitRange>[31:4]</bitRange>		
								
						</field>			
					</fields>				
				</register>					
			</registers>						
			
			
		</peripheral>
		
		<peripheral>
	<name>CMP</name>
	<description>Analog comparator</description>
	<groupName>CMP</groupName>
	<baseAddress>0x40024000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<interrupt>
	<name>CMP</name>
	<value>11</value>
	</interrupt>
	<registers>
		<register>
			<name>CTRL</name>
			<description>Comparator control register</description>
			<addressOffset>0x000</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Write as 0.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>EDGESEL</name>
					<description>This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 00 = Falling edges 01 = Rising edges 1x = Both edges</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>FALLING_EDGES</name>
							<description>Falling edges</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGES</name>
							<description>Rising edges</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>BOTH_EDGES_2</name>
							<description>Both edges</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>BOTH_EDGES_3</name>
							<description>Both edges</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Write as 0.</description>
					<bitRange>[5:5]</bitRange>
					
				</field>
				<field>
					<name>COMPSA</name>
					<description>Comparator output control</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DIRECT</name>
							<description>Comparator output  is used directly.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SYNCH</name>
							<description>Comparator output is synchronized to the bus clock for output to other modules.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Write as 0.</description>
					<bitRange>[7:7]</bitRange>
					
				</field>
				<field>
					<name>COMP_VP_SEL</name>
					<description>Selects positive voltage input</description>
					<bitRange>[10:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>VOLTAGE_LADDER_OUTPU</name>
							<description>Voltage ladder output</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ACMP_I1</name>
							<description>ACMP_I1</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ACMP_I2</name>
							<description>ACMP_I2</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INTERNAL_REFERENCE_V</name>
							<description>Internal reference voltage</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>COMP_VM_SEL</name>
					<description>Selects negative voltage input</description>
					<bitRange>[13:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>VOLTAGE_LADDER_OUTPU</name>
							<description>voltage ladder output</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ACMP_I1</name>
							<description>ACMP_I1</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ACMP_I2</name>
							<description>ACMP_I2</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INTERNAL_REFERENCE_V</name>
							<description>Internal reference voltage</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED</name>
							<description>Reserved</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Write as 0.</description>
					<bitRange>[19:14]</bitRange>
					
				</field>
				<field>
					<name>EDGECLR</name>
					<description>Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.</description>
					<bitRange>[20:20]</bitRange>
					
				</field>
				<field>
					<name>COMPSTAT</name>
					<description>Comparator status. This bit reflects the state of the comparator output.</description>
					<bitRange>[21:21]</bitRange>
					
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Write as 0.</description>
					<bitRange>[22:22]</bitRange>
					
				</field>
				<field>
					<name>COMPEDGE</name>
					<description>Comparator edge-detect status.</description>
					<bitRange>[23:23]</bitRange>
					
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Write as 0.</description>
					<bitRange>[24:24]</bitRange>
					
				</field>
				<field>
					<name>HYS</name>
					<description>Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.</description>
					<bitRange>[26:25]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NONE_THE_OUTPUT_WIL</name>
							<description>None (the output will switch as the voltages cross)</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>5_MV</name>
							<description>5 mV</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>10_MV</name>
							<description>10 mV</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>20_MV</name>
							<description>20 mV</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:27]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>LAD</name>
			<description>Voltage ladder register</description>
			<addressOffset>0x004</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>LADEN</name>
					<description>Voltage ladder enable</description>
					<bitRange>[0:0]</bitRange>
					
				</field>
				<field>
					<name>LADSEL</name>
					<description>Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref</description>
					<bitRange>[5:1]</bitRange>
					
				</field>
				<field>
					<name>LADREF</name>
					<description>Selects the reference voltage Vref for the voltage ladder:</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SUPPLY_PIN_VDD</name>
							<description>Supply pin VDD</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>VDDCMP_PIN</name>
							<description>VDDCMP pin</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Unused</description>
					<bitRange>[31:7]</bitRange>
					
				</field>
			</fields>
		</register>
	</registers>
		</peripheral>
		
		<peripheral>
			<name>FLASHCTRL</name>
			<description> Flash controller </description>
			<groupName>FLASHCTRL</groupName>
			<baseAddress>0x40040000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>FLASH_IRQ</name>
				<value>14</value>
			</interrupt>
			<registers>												
				<register>											
					<name>FLASHCFG</name>										
					<description>Flash configuration register</description>										
					<addressOffset>0x010</addressOffset>										
					<access>read-write</access>										
					<resetValue>0</resetValue>										
					<resetMask>0x00000000</resetMask>										
					<fields>										
						<field>									
							<name>FLASHTIM</name>								
							<description>Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.</description>								
							<bitRange>[1:0]</bitRange>								
							<enumeratedValues>								
								<name>ENUM</name>								
								<enumeratedValue>							
									<name>1_SYSTEM_CLOCK_FLASH</name>						
									<description>1 system clock flash access time (for system clock frequencies of up to 20 MHz).</description>						
									<value>0x0</value>						
								</enumeratedValue>							
								<enumeratedValue>							
									<name>2_SYSTEM_CLOCKS_FLAS</name>						
									<description>2 system clocks flash access time (for system clock frequencies of up to 30 MHz).</description>						
									<value>0x1</value>						
								</enumeratedValue>							
								<enumeratedValue>							
									<name>FLASHTIM_RESERVED_</name>
									<description>Reserved.</description>						
									<value>0x2</value>						
								</enumeratedValue>							
								<enumeratedValue>							
									<name>RESERVED_</name>						
									<description>Reserved.</description>						
									<value>0x3</value>						
								</enumeratedValue>							
							</enumeratedValues>								
						</field>									
						<field>									
							<name>RESERVED</name>								
							<description>Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.</description>								
							<bitRange>[31:2]</bitRange>								
														
						</field>									
					</fields>										
				</register>											
				<register>											
					<name>FMSSTART</name>										
					<description>Signature start address register</description>										
					<addressOffset>0x020</addressOffset>										
					<access>read-write</access>										
					<resetValue>0</resetValue>										
					<resetMask>0xFFFFFFFF</resetMask>										
					<fields>										
						<field>									
							<name>START</name>								
							<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>								
							<bitRange>[16:0]</bitRange>								
						</field>									
						<field>									
							<name>RESERVED</name>								
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>								
							<bitRange>[31:17]</bitRange>								
						</field>									
					</fields>										
				</register>											
				<register>											
					<name>FMSSTOP</name>										
					<description>Signature stop-address register</description>										
					<addressOffset>0x024</addressOffset>										
					<access>read-write</access>										
					<resetValue>0</resetValue>										
					<resetMask>0xFFFFFFFF</resetMask>										
					<fields>										
						<field>									
							<name>STOPA</name>								
							<description>Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes.  If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111.</description>								
							<bitRange>[16:0]</bitRange>								
														
						</field>									
						<field>									
							<name>RESERVED</name>								
							<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>								
							<bitRange>[30:17]</bitRange>								
														
						</field>									
						<field>									
							<name>STRTBIST</name>								
							<description>When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared.</description>								
							<bitRange>[31:31]</bitRange>								
														
						</field>									
					</fields>										
				</register>											
				<register>											
					<name>FMSW0</name>										
					<description>Signature Word </description>										
					<addressOffset>0x02C</addressOffset>										
					<access>read-only</access>										
					<resetValue>0</resetValue>										
					<resetMask>0x00000000</resetMask>										
					<fields>										
						<field>									
							<name>SIG</name>								
							<description>32-bit signature.</description>								
							<bitRange>[31:0]</bitRange>								
						</field>									
					</fields>										
				</register>											
			</registers>												
			
		</peripheral>


		
<peripheral>
	<name>IOCON</name>
	<description>I/O configuration (IOCON)</description>
	<groupName>IOCON</groupName>
	<baseAddress>0x40044000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<registers>
		<register>
			<name>PIO0_17</name>
			<description>I/O configuration for pin PIO0_17</description>
			<addressOffset>0x000</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_13</name>
			<description>I/O configuration for pin PIO0_13</description>
			<addressOffset>0x004</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_12</name>
			<description>I/O configuration for pin PIO0_12</description>
			<addressOffset>0x008</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_5</name>
			<description>I/O configuration for pin PIO0_5/RESET</description>
			<addressOffset>0x00C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_4</name>
			<description>I/O configuration for pin PIO0_4</description>
			<addressOffset>0x010</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_3</name>
			<description>I/O configuration for pin PIO0_3/SWCLK</description>
			<addressOffset>0x014</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input.</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_2</name>
			<description>I/O configuration for pin PIO0_2/SWDIO</description>
			<addressOffset>0x018</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input.</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_11</name>
			<description>I/O configuration for pin PIO0_11. This is the pin configuration for the true open-drain pin.</description>
			<addressOffset>0x01C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000080</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[5:0]</bitRange>
					
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[7:7]</bitRange>
					
				</field>
				<field>
					<name>I2CMODE</name>
					<description>Selects I2C mode.  Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
					<bitRange>[9:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>STANDARD_MODE</name>
							<description>Standard mode/ Fast-mode I2C.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>STANDARD_IO</name>
							<description>Standard I/O functionality</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FAST_MODE_PLUS_I2C</name>
							<description>Fast-mode Plus I2C</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED_</name>
							<description>Reserved.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[10:10]</bitRange>
					
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_10</name>
			<description>I/O configuration for pin PIO0_10. This is the pin configuration for the true open-drain pin.</description>
			<addressOffset>0x020</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000080</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[5:0]</bitRange>
					
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[7:7]</bitRange>
					
				</field>
				<field>
					<name>I2CMODE</name>
					<description>Selects I2C mode.  Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
					<bitRange>[9:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>STANDARD_MODE</name>
							<description>Standard mode/ Fast-mode I2C.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>STANDARD_IO</name>
							<description>Standard I/O functionality</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FAST_MODE_PLUS_I2C</name>
							<description>Fast-mode Plus I2C</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED_</name>
							<description>Reserved.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[10:10]</bitRange>
					
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_16</name>
			<description>I/O configuration for pin PIO0_16</description>
			<addressOffset>0x024</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_15</name>
			<description>I/O configuration for pin PIO0_15</description>
			<addressOffset>0x028</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_1</name>
			<description>I/O configuration for pin PIO0_1/ACMP_I1/CLKIN</description>
			<addressOffset>0x02C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_9</name>
			<description>I/O configuration for pin PIO0_9/XTALOUT</description>
			<addressOffset>0x034</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_8</name>
			<description>I/O configuration for pin PIO0_8/XTALIN</description>
			<addressOffset>0x038</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_7</name>
			<description>I/O configuration for pin PIO0_7</description>
			<addressOffset>0x03C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_6</name>
			<description>I/O configuration for pin PIO0_6/VDDCMP</description>
			<addressOffset>0x040</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_0</name>
			<description>I/O configuration for pin PIO0_0/ACMP_I0</description>
			<addressOffset>0x044</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
										
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PIO0_14</name>
			<description>I/O configuration for pin PIO0_14</description>
			<addressOffset>0x048</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000090</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[2:0]</bitRange>
										
					
				</field>
				<field>
					<name>MODE</name>
					<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
					<bitRange>[4:3]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>INACTIVE_NO_PULL_DO</name>
							<description>Inactive (no pull-down/pull-up resistor enabled).</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_DOWN_RESISTOR_E</name>
							<description>Pull-down resistor enabled.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PULL_UP_RESISTOR_ENA</name>
							<description>Pull-up resistor enabled.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATER_MODE_</name>
							<description>Repeater mode.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>HYS</name>
					<description>Hysteresis.</description>
					<bitRange>[5:5]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLE_</name>
							<description>Enable.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>INV</name>
					<description>Invert input</description>
					<bitRange>[6:6]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>INPUT_NOT_INVERTED_</name>
							<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_INVERTED_HIGH</name>
							<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[9:7]</bitRange>
										
					
				</field>
				<field>
					<name>OD</name>
					<description>Open-drain mode.</description>
					<bitRange>[10:10]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>DISABLE_</name>
							<description>Disable.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OPEN_DRAIN_MODE_ENAB</name>
							<description>Open-drain mode enabled.  This is not a true open-drain mode.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>S_MODE</name>
					<description>Digital filter sample mode.</description>
					<bitRange>[12:11]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>BYPASS_INPUT_FILTER_</name>
							<description>Bypass input filter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>1_CLOCK_CYCLE_INPUT</name>
							<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>2_CLOCK_CYCLES_INPU</name>
							<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCK_CYCLES_INPU</name>
							<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLK_DIV</name>
					<description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
					<bitRange>[15:13]</bitRange>
										
					<enumeratedValues>
					<name>ENUM</name>
										
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV0_</name>
							<description>IOCONFILTRCLKDIV0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV1_</name>
							<description>IOCONFILTRCLKDIV1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV2_</name>
							<description>IOCONFILTRCLKDIV2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV3_</name>
							<description>IOCONFILTRCLKDIV3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV4_</name>
							<description>IOCONFILTRCLKDIV4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV5_</name>
							<description>IOCONFILTRCLKDIV5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IOCONFILTRCLKDIV6_</name>
							<description>IOCONFILTRCLKDIV6.</description>
							<value>0x6</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:16]</bitRange>
										
					
				</field>
			</fields>
		</register>
										
										
	</registers>
</peripheral>


		<peripheral>
			<name>SYSCON</name>
			<description>System configuration (SYSCON)</description>
			<groupName>SYSCON</groupName>
			<baseAddress>0x40048000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>BOD</name>
				<value>13</value>
			</interrupt>
		<registers>						
	<register>					
		<name>SYSMEMREMAP</name>				
		<description>System memory remap</description>				
		<addressOffset>0x000</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x2</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>MAP</name>		
				<description>System memory remap. Value 0x3 is reserved.</description>		
				<bitRange>[1:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>BOOT_LOADER_MODE_IN</name>
						<description>Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>USER_RAM_MODE_INTER</name>
						<description>User RAM Mode. Interrupt vectors are re-mapped to Static RAM.</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>USER_FLASH_MODE_INT</name>
						<description>User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.</description>
						<value>0x2</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:2]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PRESETCTRL</name>				
		<description>Peripheral reset control</description>				
		<addressOffset>0x004</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00001FFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SPI0_RST_N</name>		
				<description>SPI0 reset control</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_SPI0_RESE</name>
						<description>Assert the SPI0 reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_SPI0_RESET</name>
						<description>Clear the SPI0 reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SPI1_RST_N</name>		
				<description>SPI1 reset control</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_SPI1_RESE</name>
						<description>Assert the SPI1 reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_SPI1_RESET</name>
						<description>Clear the SPI1 reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>UARTFRG_RST_N</name>		
				<description>UART fractional baud rate generator (UARTFRG) reset control</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_UARTFRG_R</name>
						<description>Assert the UARTFRG reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_UARTFRG_RE</name>
						<description>Clear the UARTFRG reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>USART0_RST_N</name>		
				<description>USART0 reset control</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_USART0_RE</name>
						<description>Assert the USART0 reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_USART0_RES</name>
						<description>Clear the USART0 reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>UART1_RST_N</name>		
				<description>U1ART1 reset control</description>		
				<bitRange>[4:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_UART_RESE</name>
						<description>Assert the UART reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_UART1_RESE</name>
						<description>Clear the UART1 reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>UART2_RST_N</name>		
				<description>UART2 reset control</description>		
				<bitRange>[5:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_UART2_RES</name>
						<description>Assert the UART2 reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_UART2_RESE</name>
						<description>Clear the UART2 reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>I2C_RST_N</name>		
				<description>I2C reset control</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_I2C_RESET</name>
						<description>Assert the I2C reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_I2C_RESET_</name>
						<description>Clear the I2C reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>MRT_RST_N</name>		
				<description>Multi-rate timer (MRT) reset control</description>		
				<bitRange>[7:7]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_MRT_RESET</name>
						<description>Assert the MRT reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_MRT_RESET_</name>
						<description>Clear the MRT reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SCT_RST_N</name>		
				<description>SCT reset control</description>		
				<bitRange>[8:8]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_SCT_RESET</name>
						<description>Assert the SCT reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_SCT_RESET_</name>
						<description>Clear the SCT reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WKT_RST_N</name>		
				<description>Self wake-up timer (WKT) reset control</description>		
				<bitRange>[9:9]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_WKT_RESET</name>
						<description>Assert the WKT reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_WKT_RESET_</name>
						<description>Clear the WKT reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>GPIO_RST_N</name>		
				<description>GPIO and GPIO pin interrupt reset control</description>		
				<bitRange>[10:10]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_GPIO_RESE</name>
						<description>Assert the GPIO reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_GPIO_RESET</name>
						<description>Clear the GPIO reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>FLASH_RST_N</name>		
				<description>Flash controller reset control</description>		
				<bitRange>[11:11]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_FLASH_CON</name>
						<description>Assert the flash controller reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_FLASH_CONT</name>
						<description>Clear the flash controller reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>ACMP_RST_N</name>		
				<description>Analog comparator reset control</description>		
				<bitRange>[12:12]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASSERT_THE_ANALOG_CO</name>
						<description>Assert the analog comparator reset.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLEAR_THE_ANALOG_COM</name>
						<description>Clear the analog comparator controller reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:12]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSPLLCTRL</name>				
		<description>System PLL control</description>				
		<addressOffset>0x008</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>MSEL</name>		
				<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32</description>		
				<bitRange>[4:0]</bitRange>		
					
			</field>			
			<field>			
				<name>PSEL</name>		
				<description>Post divider ratio P. The division ratio is 2 x P.</description>		
				<bitRange>[6:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>P_EQ_1</name>
						<description>P = 1</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>P_EQ_2</name>
						<description>P = 2</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>P_EQ_4</name>
						<description>P = 4</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>P_EQ_8</name>
						<description>P = 8</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Do not write ones to reserved bits.</description>		
				<bitRange>[31:7]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSPLLSTAT</name>				
		<description>System PLL status</description>				
		<addressOffset>0x00C</addressOffset>				
		<access>read-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>LOCK</name>		
				<description>PLL lock status</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>PLL_NOT_LOCKED</name>
						<description>PLL not locked</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PLL_LOCKED</name>
						<description>PLL locked</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:1]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSOSCCTRL</name>				
		<description>System oscillator control</description>				
		<addressOffset>0x020</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>BYPASS</name>		
				<description>Bypass system oscillator</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED_OSCILLATOR</name>
						<description>Disabled. Oscillator is not bypassed.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED_PLL_INPUT_</name>
						<description>Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>FREQRANGE</name>		
				<description>Determines frequency range for Low-power oscillator.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>1_20_MHZ_FREQUENCY</name>
						<description>1 - 20 MHz frequency range.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>15_25_MHZ_FREQUENC</name>
						<description>15 - 25 MHz frequency range</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:2]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>WDTOSCCTRL</name>				
		<description>Watchdog oscillator control</description>				
		<addressOffset>0x024</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x0A0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIVSEL</name>		
				<description>Select divider for Fclkana.  wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64</description>		
				<bitRange>[4:0]</bitRange>		
					
			</field>			
			<field>			
				<name>FREQSEL</name>		
				<description>Select watchdog oscillator analog output frequency (Fclkana).</description>		
				<bitRange>[8:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>0_6_MHZ</name>
						<description>0.6 MHz</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>1_05_MHZ</name>
						<description>1.05 MHz</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>1_4_MHZ</name>
						<description>1.4 MHz</description>
						<value>0x3</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>1_75_MHZ</name>
						<description>1.75 MHz</description>
						<value>0x4</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>2_1_MHZ</name>
						<description>2.1 MHz</description>
						<value>0x5</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>2_4_MHZ</name>
						<description>2.4 MHz</description>
						<value>0x6</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>2_7_MHZ</name>
						<description>2.7 MHz</description>
						<value>0x7</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>3_0_MHZ</name>
						<description>3.0 MHz</description>
						<value>0x8</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>3_25_MHZ</name>
						<description>3.25 MHz</description>
						<value>0x9</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>3_5_MHZ</name>
						<description>3.5 MHz</description>
						<value>0xA</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>3_75_MHZ</name>
						<description>3.75 MHz</description>
						<value>0xB</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>4_0_MHZ</name>
						<description>4.0 MHz</description>
						<value>0xC</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>4_2_MHZ</name>
						<description>4.2 MHz</description>
						<value>0xD</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>4_4_MHZ</name>
						<description>4.4 MHz</description>
						<value>0xE</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>4_6_MHZ</name>
						<description>4.6 MHz</description>
						<value>0xF</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:9]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSRSTSTAT</name>				
		<description>System reset status register</description>				
		<addressOffset>0x030</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>POR</name>		
				<description>POR reset status</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_POR_DETECTED</name>
						<description>No POR detected</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POR_DETECTED_WRITIN</name>
						<description>POR detected. Writing a one clears this reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>EXTRST</name>		
				<description>Status of the external RESET pin. External reset status.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_RESET_EVENT_DETEC</name>
						<description>No reset event detected.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RESET_DETECTED_WRIT</name>
						<description>Reset detected. Writing a one clears this reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WDT</name>		
				<description>Status of the Watchdog reset</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_WDT_RESET_DETECTE</name>
						<description>No WDT reset detected</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>WDT_RESET_DETECTED_</name>
						<description>WDT reset detected. Writing a one clears this reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>BOD</name>		
				<description>Status of the Brown-out detect reset</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_BOD_RESET_DETECTE</name>
						<description>No BOD reset detected</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>BOD_RESET_DETECTED_</name>
						<description>BOD reset detected. Writing a one clears this reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SYSRST</name>		
				<description>Status of the software system reset</description>		
				<bitRange>[4:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_SYSTEM_RESET_DETE</name>
						<description>No System reset detected</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>SYSTEM_RESET_DETECTE</name>
						<description>System reset detected. Writing a one clears this reset.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:5]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSPLLCLKSEL</name>				
		<description>System PLL clock source select</description>				
		<addressOffset>0x040</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SEL</name>		
				<description>System PLL clock source</description>		
				<bitRange>[1:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>IRC</name>
						<description>IRC</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CRYSTAL_OSCILLATOR_</name>
						<description>Crystal Oscillator (SYSOSC)</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RESERVED_</name>
						<description>Reserved.</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CLKIN_EXTERNAL_CLOC</name>
						<description>CLKIN. External clock input.</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:2]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSPLLCLKUEN</name>				
		<description>System PLL clock source update enable</description>				
		<addressOffset>0x044</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>ENA</name>		
				<description>Enable system PLL clock source update</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_CHANGE</name>
						<description>No change</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>UPDATE_CLOCK_SOURCE</name>
						<description>Update clock source</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:1]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>MAINCLKSEL</name>				
		<description>Main clock source select</description>				
		<addressOffset>0x070</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SEL</name>		
				<description>Clock source for main clock</description>		
				<bitRange>[1:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>IRC_OSCILLATOR</name>
						<description>IRC Oscillator</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PLL_INPUT</name>
						<description>PLL input</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>WATCHDOG_OSCILLATOR</name>
						<description>Watchdog oscillator</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>PLL_OUTPUT</name>
						<description>PLL output</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:2]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>MAINCLKUEN</name>				
		<description>Main clock source update enable</description>				
		<addressOffset>0x074</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>ENA</name>		
				<description>Enable main clock source update</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_CHANGE</name>
						<description>No change</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>UPDATE_CLOCK_SOURCE</name>
						<description>Update clock source</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:1]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSAHBCLKDIV</name>				
		<description>System clock divider</description>				
		<addressOffset>0x078</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0x00000000</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>System AHB clock divider values 0: System clock disabled.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSAHBCLKCTRL</name>				
		<description>System clock control</description>				
		<addressOffset>0x080</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x1F</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SYS</name>		
				<description>Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>RESERVED</name>
						<description>Reserved</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>ROM</name>		
				<description>Enables clock for ROM.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RAM</name>		
				<description>Enables clock for SRAM.</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>FLASHREG</name>		
				<description>Enables clock for flash register interface.</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>FLASH</name>		
				<description>Enables clock for flash.</description>		
				<bitRange>[4:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>I2C</name>		
				<description>Enables clock for I2C.</description>		
				<bitRange>[5:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>GPIO</name>		
				<description>Enables clock for GPIO port registers and GPIO pin interrupt registers.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SWM</name>		
				<description>Enables clock for switch matrix.</description>		
				<bitRange>[7:7]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SCT</name>		
				<description>Enables clock for state configurable timer.</description>		
				<bitRange>[8:8]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WKT</name>		
				<description>Enables clock for self wake-up timer.</description>		
				<bitRange>[9:9]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>MRT</name>		
				<description>Enables clock for multi-rate timer.</description>		
				<bitRange>[10:10]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SPI0</name>		
				<description>Enables clock for SPI0.</description>		
				<bitRange>[11:11]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SPI1</name>		
				<description>Enables clock for SPI1.</description>		
				<bitRange>[12:12]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>CRC</name>		
				<description>Enables clock for CRC.</description>		
				<bitRange>[13:13]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>UART0</name>		
				<description>Enables clock for UART0.</description>		
				<bitRange>[14:14]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>UART1</name>		
				<description>Enables clock for UART1.</description>		
				<bitRange>[15:15]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>UART2</name>		
				<description>Enables clock for UART2.</description>		
				<bitRange>[16:16]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WWDT</name>		
				<description>Enables clock for WWDT.</description>		
				<bitRange>[17:17]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>IOCON</name>		
				<description>Enables clock for IOCON block.</description>		
				<bitRange>[18:18]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>ACMP</name>		
				<description>Enables clock to analog comparator.</description>		
				<bitRange>[19:19]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE</name>
						<description>Disable</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE</name>
						<description>Enable</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:20]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>UARTCLKDIV</name>				
		<description>UART clock divider</description>				
		<addressOffset>0x094</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>UART clock divider values.  0: Clock disabled.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>CLKOUTSEL</name>				
		<description>CLKOUT clock source select</description>				
		<addressOffset>0x0E0</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>SEL</name>		
				<description>CLKOUT clock source</description>		
				<bitRange>[1:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>IRC_OSCILLATOR</name>
						<description>IRC oscillator</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CRYSTAL_OSCILLATOR_</name>
						<description>Crystal oscillator (SYSOSC)</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>WATCHDOG_OSCILLATOR</name>
						<description>Watchdog oscillator</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>MAIN_CLOCK</name>
						<description>Main clock</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:2]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>CLKOUTUEN</name>				
		<description>CLKOUT clock source update enable</description>				
		<addressOffset>0x0E4</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>ENA</name>		
				<description>Enable CLKOUT clock source update</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_CHANGE</name>
						<description>No change</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>UPDATE_CLOCK_SOURCE</name>
						<description>Update clock source</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:1]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>CLKOUTDIV</name>				
		<description>CLKOUT clock divider</description>				
		<addressOffset>0x0E8</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>CLKOUT clock divider values 0: Disable CLKOUT clock divider.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>UARTFRGDIV</name>				
		<description>UART fractional generator divider value</description>				
		<addressOffset>0x0F0</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>UARTFRGMULT</name>				
		<description>UART fractional generator multiplier value</description>				
		<addressOffset>0x0F4</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>MULT</name>		
				<description>Numerator of the fractional divider. MULT is equal to the programmed value.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>EXTTRACECMD</name>				
		<description>External trace buffer command register</description>				
		<addressOffset>0x0FC</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>START</name>		
				<description>Trace start command</description>		
				<bitRange>[0:0]</bitRange>		
			</field>			
			<field>			
				<name>STOP</name>		
				<description>Trace stop command</description>		
				<bitRange>[1:1]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:2]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PIOPORCAP0</name>				
		<description>POR captured PIO status 0</description>				
		<addressOffset>0x100</addressOffset>				
		<access>read-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0x00000000</resetMask>				
		<fields>				
			<field>			
				<name>PIOSTAT</name>		
				<description>State of PIO0_17 through PIO0_0 at power-on reset</description>		
				<bitRange>[17:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[31:18]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV6</name>				
		<description>Peripheral clock 6 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x134</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV5</name>				
		<description>Peripheral clock 5 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x138</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV4</name>				
		<description>Peripheral clock 4 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x13C</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV3</name>				
		<description>Peripheral clock 3 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x140</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV2</name>				
		<description>Peripheral clock 2 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x144</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV1</name>				
		<description>Peripheral clock 1 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x148</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>IOCONCLKDIV0</name>				
		<description>Peripheral clock 0 to the IOCON block for programmable glitch filter</description>				
		<addressOffset>0x14C</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000000</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>DIV</name>		
				<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255.</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>BODCTRL</name>				
		<description>Brown-Out Detect</description>				
		<addressOffset>0x150</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>BODRSTLEV</name>		
				<description>BOD reset level</description>		
				<bitRange>[1:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>LEVEL_0_THE_RESET_A</name>
						<description>Level 0: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is .</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LEVEL_1_THE_RESET_A</name>
						<description>Level 1: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is .</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LEVEL_2_THE_RESET_A</name>
						<description>Level 2: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is .</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LEVEL_3_THE_RESET_A</name>
						<description>Level 3: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is.</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>BODINTVAL</name>		
				<description>BOD interrupt level</description>		
				<bitRange>[3:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>LEVEL_0_THE_INTERRU</name>
						<description>Level 0: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LEVEL_1THE_INTERRUP</name>
						<description>Level 1:The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is .</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LEVEL_2_THE_INTERRU</name>
						<description>Level 2: The interrupt assertion threshold voltage is  ; the interrupt de-assertion threshold voltage is .</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LEVEL_3_THE_INTERRU</name>
						<description>Level 3: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is .</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>BODRSTENA</name>		
				<description>BOD reset enable</description>		
				<bitRange>[4:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLE_RESET_FUNCTI</name>
						<description>Disable reset function.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLE_RESET_FUNCTIO</name>
						<description>Enable reset function.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:5]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>SYSTCKCAL</name>				
		<description>System tick counter calibration</description>				
		<addressOffset>0x154</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>CAL</name>		
				<description>System tick timer calibration value</description>		
				<bitRange>[25:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:26]</bitRange>		
			</field>			
		</fields>				
	</register>					
						
	<register>					
		<name>IRQLATENCY</name>				
		<description>IQR delay. Allows trade-off between interrupt latency and determinism.</description>				
		<addressOffset>0x170</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x00000010</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>LATENCY</name>		
				<description>8-bit latency value</description>		
				<bitRange>[7:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>NMISRC</name>				
		<description>NMI Source Control</description>				
		<addressOffset>0x174</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>IRQNO</name>		
				<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 58 for the list of interrupt sources and their IRQ numbers.</description>		
				<bitRange>[4:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[30:5]</bitRange>		
			</field>			
			<field>			
				<name>NMIEN</name>		
				<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>		
				<bitRange>[31:31]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<dim>8</dim>				
		<dimIncrement>0x4</dimIncrement>				
		<dimIndex>0-7</dimIndex>				
		<name>PINTSEL%s</name>				
		<description>GPIO Pin Interrupt Select register 0</description>				
		<addressOffset>0x178</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>INTPIN</name>		
				<description>Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).</description>		
				<bitRange>[5:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:6]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>STARTERP0</name>				
		<description>Start logic 0 pin wake-up enable register</description>				
		<addressOffset>0x204</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>PINT0</name>		
				<description>GPIO pin interrupt 0 wake-up</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT1</name>		
				<description>GPIO pin interrupt 1 wake-up</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT2</name>		
				<description>GPIO pin interrupt 2 wake-up</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT3</name>		
				<description>GPIO pin interrupt 3 wake-up</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT4</name>		
				<description>GPIO pin interrupt 4 wake-up</description>		
				<bitRange>[4:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT5</name>		
				<description>GPIO pin interrupt 5 wake-up</description>		
				<bitRange>[5:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT6</name>		
				<description>GPIO pin interrupt 6 wake-up</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PINT7</name>		
				<description>GPIO pin interrupt 7 wake-up</description>		
				<bitRange>[7:7]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:8]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>STARTERP1</name>				
		<description>Start logic 1 interrupt wake-up enable register</description>				
		<addressOffset>0x214</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[11:0]</bitRange>		
					
			</field>			
			<field>			
				<name>WWDT</name>		
				<description>WWDT interrupt wake-up</description>		
				<bitRange>[12:12]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>BOD</name>		
				<description>BOD interrupt wake-up</description>		
				<bitRange>[13:13]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[14:14]</bitRange>		
					
			</field>			
			<field>			
				<name>WKT</name>		
				<description>Self wake-up timer interrupt wake-up</description>		
				<bitRange>[15:15]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED</name>
						<description>Disabled</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED</name>
						<description>Enabled</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PDSLEEPCFG</name>				
		<description>Power-down states in deep-sleep mode</description>				
		<addressOffset>0x230</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xFFFF</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>BOD_PD</name>		
				<description>BOD power-down control for Deep-sleep and Power-down mode</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WDTOSC_PD</name>		
				<description>Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[15:7]</bitRange>		
					
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:7]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PDAWAKECFG</name>				
		<description>Power-down states for wake-up from deep-sleep</description>				
		<addressOffset>0x234</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xEDF0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>IRCOUT_PD</name>		
				<description>IRC oscillator output wake-up configuration</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>IRC_PD</name>		
				<description>IRC oscillator power-down wake-up configuration</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>FLASH_PD</name>		
				<description>Flash wake-up configuration</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>BOD_PD</name>		
				<description>BOD wake-up configuration</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[4:4]</bitRange>		
					
			</field>			
			<field>			
				<name>SYSOSC_PD</name>		
				<description>Crystal oscillator wake-up configuration</description>		
				<bitRange>[5:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WDTOSC_PD</name>		
				<description>Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SYSPLL_PD</name>		
				<description>System PLL wake-up configuration</description>		
				<bitRange>[7:7]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Always write these bits as 0b1101</description>		
				<bitRange>[11:8]</bitRange>		
					
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Always write these bits as 0b110</description>		
				<bitRange>[14:12]</bitRange>		
					
			</field>			
			<field>			
				<name>ACMP</name>		
				<description>Analog comparator wake-up configuration</description>		
				<bitRange>[15:15]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:16]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>PDRUNCFG</name>				
		<description>Power configuration register</description>				
		<addressOffset>0x238</addressOffset>				
		<access>read-write</access>				
		<resetValue>0xEDF0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>IRCOUT_PD</name>		
				<description>IRC oscillator output power</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>IRC_PD</name>		
				<description>IRC oscillator power down</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>FLASH_PD</name>		
				<description>Flash power down</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>BOD_PD</name>		
				<description>BOD power down</description>		
				<bitRange>[3:3]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved.</description>		
				<bitRange>[4:4]</bitRange>		
					
			</field>			
			<field>			
				<name>SYSOSC_PD</name>		
				<description>Crystal oscillator power down</description>		
				<bitRange>[5:5]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>WDTOSC_PD</name>		
				<description>Watchdog oscillator power down. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>SYSPLL_PD</name>		
				<description>System PLL power down</description>		
				<bitRange>[7:7]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Always write these bits as 0b1101</description>		
				<bitRange>[11:8]</bitRange>		
					
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Always write these bits as 0b110</description>		
				<bitRange>[14:12]</bitRange>		
					
			</field>			
			<field>			
				<name>ACMP</name>		
				<description>Analog comparator power down</description>		
				<bitRange>[15:15]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>POWERED</name>
						<description>Powered</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>POWERED_DOWN</name>
						<description>Powered down</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved</description>		
				<bitRange>[31:16]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>DEVICE_ID</name>				
		<description>Device ID</description>				
		<addressOffset>0x3F4</addressOffset>				
		<access>read-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0x00000000</resetMask>				
		<fields>				
			<field>			
				<name>DEVICEID</name>		
				<description>TBD</description>		
				<bitRange>[31:0]</bitRange>		
			</field>			
		</fields>				
	</register>					
</registers>						
										

		</peripheral>
		<peripheral>
	<name>I2C</name>
	<description>I2C-bus interface</description>
	<groupName>I2C</groupName>
	<baseAddress>0x40050000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<interrupt>
	<name>I2C</name>
	<value>8</value>
	</interrupt>
	<registers>
		<register>
			<name>CFG</name>
			<description>Configuration for shared functions.</description>
			<addressOffset>0x00</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MSTEN</name>
					<description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_THE_I2C_MA</name>
							<description>Disabled. The I2C Master function is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_THE_I2C_MAS</name>
							<description>Enabled. The I2C Master function is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVEN</name>
					<description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
					<bitRange>[1:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_THE_I2C_SL</name>
							<description>Disabled. The I2C slave function is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_THE_I2C_SLA</name>
							<description>Enabled. The I2C slave function is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONEN</name>
					<description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
					<bitRange>[2:2]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_THE_I2C_MO</name>
							<description>Disabled. The I2C monitor function is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_THE_I2C_MON</name>
							<description>Enabled. The I2C monitor function is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>TIMEOUTEN</name>
					<description>I2C bus Time-out Enable. When disabled, timeout flags will be automatically cleared.</description>
					<bitRange>[3:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_TIME_OUT_F</name>
							<description>Disabled. Time-out function is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_TIME_OUT_FU</name>
							<description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one timeout will be used in a system.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONCLKSTR</name>
					<description>Monitor function Clock Stretching.</description>
					<bitRange>[4:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_THE_MONITO</name>
							<description>Disabled. The monitor function will not perform clock stretching. Software may not always be able to read data provided by the monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_THE_MONITOR</name>
							<description>Enabled. The monitor function will perform clock stretching in order to ensure that software can read all incoming data supplied by the monitor function.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:5]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>STAT</name>
			<description>Status register for Master, Slave, and Monitor functions.</description>
			<addressOffset>0x04</addressOffset>
			<access>read-write</access>
			<resetValue>0x000801</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MSTPENDING</name>
					<description>Master Pending. Indicates whether the Master function needs software service. This flag will cause an interrupt when set if enabled via the INTENSET register.  The MSTPENDING flag is automatically cleared when a 1 is written to the MSTCONTINUE bit in the MSTCTL register.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_SERVICE_NEEDED_T</name>
							<description>No service needed. The Master function does not currently need service.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SERVICE_NEEDED_THE_</name>
							<description>Service needed. The Master function needs service. Information on what is needed can be found in the adjacent MSTSTATE field.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MSTSTATE</name>
					<description>Master State code. Each value of this field indicates a specific required service for the Master function.  All other values are reserved.</description>
					<bitRange>[3:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>IDLE_THE_MASTER_FUN</name>
							<description>Idle. The Master function is available to be used for a new transaction.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RECEIVE_READY_RECEI</name>
							<description>Receive ready. Received data  available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>TRANSMIT_READY_DATA</name>
							<description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ADDRESS_SLAVE_NACKE</name>
							<description>Address. Slave Nacked address.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>DATA_SLAVE_NACKED_T</name>
							<description>Data. Slave Nacked transmitted data.</description>
							<value>0x4</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MSTARBLOSS</name>
					<description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
					<bitRange>[4:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_LOSS_NO_ARBITRAT</name>
							<description>No loss. No Arbitration Loss has occurred.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ARBITRATION_LOSS_TH</name>
							<description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[5:5]</bitRange>
					
				</field>
				<field>
					<name>MSTSTSTPERR</name>
					<description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MstContinue.</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_STARTSTOP_ERROR_</name>
							<description>No Start/Stop Error has occurred.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>STARTSTOP_ERROR_HAS</name>
							<description>Start/stop error has occurred. The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[7:7]</bitRange>
					
				</field>
				<field>
					<name>SLVPENDING</name>
					<description>Slave Pending. Indicates whether the Slave function needs software service. This flag will cause an interrupt when set if enabled via INTENSET.  The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register.</description>
					<bitRange>[8:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_SERVICE_NEEDED_T</name>
							<description>No service needed. The Slave function does not currently need service.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SERVICE_NEEDED_THE_</name>
							<description>Service needed. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVSTATE</name>
					<description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved.</description>
					<bitRange>[10:9]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>RECEIVED_ADDRESS_PL</name>
							<description>Received. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>DATA_AVAILABLE_RECE</name>
							<description>Data available. Received data is available (Slave Receiver mode).</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>DATA_READY_FOR_TRANS</name>
							<description>Data ready for transmit. Data can be transmitted (Slave Transmitter mode).</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED_</name>
							<description>Reserved.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVNOTSTR</name>
					<description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
					<bitRange>[11:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>STRETCHING_THE_SLAV</name>
							<description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>NOT_STRETCHING_THE_</name>
							<description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVIDX</name>
					<description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
					<bitRange>[13:12]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SLAVE_ADDRESS_0_WAS_</name>
							<description>Slave address 0 was matched.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SLAVE_ADDRESS_1_WAS_</name>
							<description>Slave address 1 was matched.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SLAVE_ADDRESS_2_WAS_</name>
							<description>Slave address 2 was matched.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SLAVE_ADDRESS_3_WAS_</name>
							<description>Slave address 3 was matched.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVSEL</name>
					<description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to Nack a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software Nacks data.</description>
					<bitRange>[14:14]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NOT_SELECTED_THE_SL</name>
							<description>Not selected. The Slave function is not currently selected.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SELECTED_THE_SLAVE_</name>
							<description>Selected. The Slave function is currently selected.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVDESEL</name>
					<description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
					<bitRange>[15:15]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NOT_DESELECTED_THE_</name>
							<description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>DESELECTED_THE_SLAV</name>
							<description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONRDY</name>
					<description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
					<bitRange>[16:16]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_DATA_THE_MONITOR</name>
							<description>No data. The Monitor function does not currently have data available.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>DATA_WAITING_THE_MO</name>
							<description>Data waiting. The Monitor function has data waiting to be read.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONOV</name>
					<description>Monitor Overflow flag.</description>
					<bitRange>[17:17]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_OVERRUN_MONITOR_</name>
							<description>No overrun. Monitor data has not overrun.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>OVERRUN_A_MONITOR_D</name>
							<description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONACTIVE</name>
					<description>Monitor Active flag. This flag indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
					<bitRange>[18:18]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INACTIVE_THE_MONITO</name>
							<description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ACTIVE_THE_MONITOR_</name>
							<description>Active. The Monitor function considers the I2C bus to be active.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONIDLE</name>
					<description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register . The flag can be cleared by writing a 1 to this bit.</description>
					<bitRange>[19:19]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NOT_IDLE_THE_I2C_BU</name>
							<description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IDLE_THE_I2C_BUS_HA</name>
							<description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[23:20]</bitRange>
					
				</field>
				<field>
					<name>EVENTTIMEOUT</name>
					<description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The case of SCL remaining low longer than TIMEOUT is not reported by this flag, it is reported in by the SCL Time-out flag. The flag is cleared by writing a 1 to this bit.</description>
					<bitRange>[24:24]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_TIME_OUT_I2C_BUS</name>
							<description>No time-out. I2C bus events have not caused a timeout.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_TIME_OUT_THE_</name>
							<description>Event time-out. The time between I2C bus events has been longer than the time specified by the I2C Timeout register.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SCLTIMEOUT</name>
					<description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
					<bitRange>[25:25]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_TIME_OUT_SCL_LOW</name>
							<description>No time-out. SCL low time has not caused a timeout.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>TIME_OUT_SCL_LOW_TI</name>
							<description>Time-out. SCL low time has caused a timeout.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:26]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>INTENSET</name>
			<description>Interrupt Enable Set and read register.</description>
			<addressOffset>0x08</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MSTPENDINGEN</name>
					<description>Master Pending interrupt Enable.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The MstPending interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED</name>
							<description>The MstPending interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[3:1]</bitRange>
					
				</field>
				<field>
					<name>MSTARBLOSSEN</name>
					<description>Master Arbitration Loss interrupt Enable.</description>
					<bitRange>[4:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The MstArbLoss interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_MSTARBLOSS_INTER</name>
							<description>The MstArbLoss interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[5:5]</bitRange>
					
				</field>
				<field>
					<name>MSTSTSTPERREN</name>
					<description>Master Start/Stop Error interrupt Enable.</description>
					<bitRange>[6:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The MstStStpErr interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_MSTSTSTPERR_INTE</name>
							<description>The MstStStpErr interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[7:7]</bitRange>
					
				</field>
				<field>
					<name>SLVPENDINGEN</name>
					<description>Slave Pending interrupt Enable.</description>
					<bitRange>[8:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The SlvPending interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_SLVPENDING_INTER</name>
							<description>The SlvPending interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[10:9]</bitRange>
					
				</field>
				<field>
					<name>SLVNOTSTREN</name>
					<description>Slave Not Stretching interrupt Enable.</description>
					<bitRange>[11:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The SlvNotStr interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_SLVNOTSTR_INTERR</name>
							<description>The SlvNotStr interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[14:12]</bitRange>
					
				</field>
				<field>
					<name>SLVDESELEN</name>
					<description>Slave Deselect interrupt Enable.</description>
					<bitRange>[15:15]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The SlvDeSel interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_SLVDESEL_INTERRU</name>
							<description>The SlvDeSel interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONRDYEN</name>
					<description>Monitor data Ready interrupt Enable.</description>
					<bitRange>[16:16]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The MonRdy interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_MONRDY_INTERRUPT</name>
							<description>The MonRdy interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONOVEN</name>
					<description>Monitor Overrun interrupt Enable.</description>
					<bitRange>[17:17]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The MonOv interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_MONOV_INTERRUPT_</name>
							<description>The MonOv interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[18:18]</bitRange>
					
				</field>
				<field>
					<name>MONIDLEEN</name>
					<description>Monitor Idle interrupt Enable.</description>
					<bitRange>[19:19]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The MonIdle interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_MONIDLE_INTERRUP</name>
							<description>The MonIdle interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[23:20]</bitRange>
					
				</field>
				<field>
					<name>EVENTTIMEOUTEN</name>
					<description>Event Timeout interrupt Enable.</description>
					<bitRange>[24:24]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The Event Timeout interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_EVENT_TIMEOUT_IN</name>
							<description>The Event Timeout interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SCLTIMEOUTEN</name>
					<description>SCL Timeout interrupt Enable.</description>
					<bitRange>[25:25]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED</name>
							<description>The SCL Timeout interrupt is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_SCL_TIMEOUT_INTE</name>
							<description>The SCL Timeout interrupt is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:26]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>INTENCLR</name>
			<description>Interrupt Enable Clear register.</description>
			<addressOffset>0x0C</addressOffset>
			<access>write-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<fields>
				<field>
					<name>MSTPENDINGCLR</name>
					<description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
					<bitRange>[0:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[3:1]</bitRange>
				</field>
				<field>
					<name>MSTARBLOSSCLR</name>
					<description>Master Arbitration Loss interrupt clear.</description>
					<bitRange>[4:4]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[5:5]</bitRange>
				</field>
				<field>
					<name>MSTSTSTPERRCLR</name>
					<description>Master Start/Stop Error interrupt clear.</description>
					<bitRange>[6:6]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[7:7]</bitRange>
				</field>
				<field>
					<name>SLVPENDINGCLR</name>
					<description>Slave Pending interrupt clear.</description>
					<bitRange>[8:8]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[10:9]</bitRange>
				</field>
				<field>
					<name>SLVNOTSTRCLR</name>
					<description>Slave Not Stretching interrupt clear.</description>
					<bitRange>[11:11]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[14:12]</bitRange>
				</field>
				<field>
					<name>SLVDESELCLR</name>
					<description>Slave Deselect interrupt clear.</description>
					<bitRange>[15:15]</bitRange>
				</field>
				<field>
					<name>MONRDYCLR</name>
					<description>Monitor data Ready interrupt clear.</description>
					<bitRange>[16:16]</bitRange>
				</field>
				<field>
					<name>MONOVCLR</name>
					<description>Monitor Overrun interrupt clear.</description>
					<bitRange>[17:17]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[18:18]</bitRange>
				</field>
				<field>
					<name>MONIDLECLR</name>
					<description>Monitor Idle interrupt clear.</description>
					<bitRange>[19:19]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[23:20]</bitRange>
				</field>
				<field>
					<name>EVENTTIMEOUTCLR</name>
					<description>Event Timeout interrupt clear.</description>
					<bitRange>[24:24]</bitRange>
				</field>
				<field>
					<name>SCLTIMEOUTCLR</name>
					<description>SCL Timeout interrupt clear.</description>
					<bitRange>[25:25]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:26]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>TIMEOUT</name>
			<description>Time-out value register.</description>
			<addressOffset>0x10</addressOffset>
			<access>read-write</access>
			<resetValue>0xFFFF</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>TOMIN</name>
					<description>Timeout time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum timeout of 16 I2C function clocks and also a timeout resolution of 16 I2C function clocks.</description>
					<bitRange>[3:0]</bitRange>
				</field>
				<field>
					<name>TO</name>
					<description>Timeout time value. Specifies the timeout interval value in increments of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A timeout will occur after 65,536 counts of the I2C function clock.</description>
					<bitRange>[15:4]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>DIV</name>
			<description>Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME and SLVTIME registers.</description>
			<addressOffset>0x14</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>DIVVAL</name>
					<description>This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C function. 0x0001 = PCLK is divided by 2 before use by the I 2C function. 0x0002 = PCLK is divided by 3 before use by the I 2C function. ... 0xFFFF = PCLK is divided by 65,536 before use by the I2C function.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>INTSTAT</name>
			<description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
			<addressOffset>0x18</addressOffset>
			<access>read-only</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MSTPENDING</name>
					<description>Master Pending.</description>
					<bitRange>[0:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[3:1]</bitRange>
				</field>
				<field>
					<name>MSTARBLOSS</name>
					<description>Master Arbitration Loss flag.</description>
					<bitRange>[4:4]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[5:5]</bitRange>
				</field>
				<field>
					<name>MSTSTSTPERR</name>
					<description>Master Start/Stop Error flag.</description>
					<bitRange>[6:6]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[7:7]</bitRange>
				</field>
				<field>
					<name>SLVPENDING</name>
					<description>Slave Pending.</description>
					<bitRange>[8:8]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[10:9]</bitRange>
				</field>
				<field>
					<name>SLVNOTSTR</name>
					<description>Slave Not Stretching status.</description>
					<bitRange>[11:11]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[14:12]</bitRange>
				</field>
				<field>
					<name>SLVDESEL</name>
					<description>Slave Deselected flag.</description>
					<bitRange>[15:15]</bitRange>
				</field>
				<field>
					<name>MONRDY</name>
					<description>Monitor Ready.</description>
					<bitRange>[16:16]</bitRange>
				</field>
				<field>
					<name>MONOV</name>
					<description>Monitor Overflow flag.</description>
					<bitRange>[17:17]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[18:18]</bitRange>
				</field>
				<field>
					<name>MONIDLE</name>
					<description>Monitor Idle flag.</description>
					<bitRange>[19:19]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[23:20]</bitRange>
				</field>
				<field>
					<name>EVENTTIMEOUT</name>
					<description>Event Timeout Interrupt flag.</description>
					<bitRange>[24:24]</bitRange>
				</field>
				<field>
					<name>SCLTIMEOUT</name>
					<description>SCL Timeout Interrupt flag.</description>
					<bitRange>[25:25]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:26]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>MSTCTL</name>
			<description>Master control register.</description>
			<addressOffset>0x20</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MSTCONTINUE</name>
					<description>Master Continue. This bit is write-only.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_EFFECT_</name>
							<description>No effect.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONTINUE_INFORMS_TH</name>
							<description>Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MSTSTART</name>
					<description>Master Start control. This bit is write-only.</description>
					<bitRange>[1:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_EFFECT_</name>
							<description>No effect.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>START_A_START_WILL_</name>
							<description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MSTSTOP</name>
					<description>Master Stop control. This bit is write-only.</description>
					<bitRange>[2:2]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_EFFECT_</name>
							<description>No effect.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>STOP_A_STOP_WILL_BE</name>
							<description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a Nack to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:2]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>MSTTIME</name>
			<description>Master timing configuration.</description>
			<addressOffset>0x24</addressOffset>
			<access>read-write</access>
			<resetValue>0x77</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MSTSCLLOW</name>
					<description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
					<bitRange>[2:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>2_CLOCKS_MINIMUM_SC</name>
							<description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCKS_MINIMUM_SC</name>
							<description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>4_CLOCKS_MINIMUM_SC</name>
							<description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>5_CLOCKS_MINIMUM_SC</name>
							<description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>6_CLOCKS_MINIMUM_SC</name>
							<description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>7_CLOCKS_MINIMUM_SC</name>
							<description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>8_CLOCKS_MINIMUM_SC</name>
							<description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>9_CLOCKS_MINIMUM_SC</name>
							<description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MSTSCLHIGH</name>
					<description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
					<bitRange>[6:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>2_CLOCKS_MINIMUM_SC</name>
							<description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>3_CLOCKS_MINIMUM_SC</name>
							<description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>4_CLOCKS_MINIMUM_SC</name>
							<description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>5_CLOCKS_MINIMUM_SC</name>
							<description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>6_CLOCKS_MINIMUM_SC</name>
							<description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>7_CLOCKS_MINIMUM_SC</name>
							<description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>8_CLOCKS_MINIMUM_SC</name>
							<description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>9_CLOCKS_MINIMUM_SC</name>
							<description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:7]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>MSTDAT</name>
			<description>Combined Master receiver and transmitter data register.</description>
			<addressOffset>0x28</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<readAction>modify</readAction>
			<fields>
				<field>
					<name>DATA</name>
					<description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>SLVCTL</name>
			<description>Slave control register.</description>
			<addressOffset>0x40</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SlvContinue</name>
					<description>Slave Continue.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_EFFECT_</name>
							<description>No effect.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONTINUE_INFORMS_TH</name>
							<description>Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SlvNack</name>
					<description>Slave Nack.</description>
					<bitRange>[1:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_EFFECT_</name>
							<description>No effect.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>NACK_CAUSES_THE_SLA</name>
							<description>Nack. Causes the Slave function to Nack the master when the slave is receiving data from the master (Slave Receiver mode).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:2]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>SLVDAT</name>
			<description>Combined Slave receiver and transmitter data register.</description>
			<addressOffset>0x44</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<readAction>modify</readAction>
			<fields>
				<field>
					<name>DATA</name>
					<description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<dim>4</dim>
			<dimIncrement>0x4</dimIncrement>
			<dimIndex>0-3</dimIndex>
			<name>SLVADR%s</name>
			<description>Slave address 0.</description>
			<addressOffset>0x48</addressOffset>
			<access>read-write</access>
			<resetValue>0x01</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SADISABLE</name>
					<description>Slave Address n Disable.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>ENABLED_SLAVE_ADDRE</name>
							<description>Enabled. Slave Address n is enabled and will be recognized with any changes specified by the SLVQUAL0 register.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IGNORED_SLAVE_ADDRES</name>
							<description>Ignored Slave Address n is ignored.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVADR</name>
					<description>Seven bit slave address that is compared to received addresses if enabled.</description>
					<bitRange>[7:1]</bitRange>
					
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:8]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>SLVQUAL0</name>
			<description>Slave Qualification for address 0.</description>
			<addressOffset>0x58</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>QUALMODE0</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>MASK</name>
							<description>The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_SLVQUAL0_FIELD_I</name>
							<description>The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SLVQUAL0</name>
					<description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] less or equal than  received address less or equal than SLVQUAL0[7:1]).</description>
					<bitRange>[7:1]</bitRange>
					
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:8]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>MONRXDAT</name>
			<description>Monitor receiver data register.</description>
			<addressOffset>0x80</addressOffset>
			<access>read-only</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MONRXDAT</name>
					<description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins, and adds indication of Start, Repeated Start, and data Nack.</description>
					<bitRange>[7:0]</bitRange>
					
				</field>
				<field>
					<name>MONSTART</name>
					<description>Monitor Received Start.</description>
					<bitRange>[8:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_DETECT_THE_MONIT</name>
							<description>No detect. The monitor function has not detected a Start event on the I2C bus.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>START_DETECT_THE_MO</name>
							<description>Start detect. The monitor function has detected a Start event on the I2C bus.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONRESTART</name>
					<description>Monitor Received Repeated Start.</description>
					<bitRange>[9:9]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_START_DETECT_THE</name>
							<description>No start detect. The monitor function has not detected a Repeated Start event on the I2C bus.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REPEATED_START_DETEC</name>
							<description>Repeated start detect. The monitor function has detected a Repeated Start event on the I 2C bus.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>MONNACK</name>
					<description>Monitor Received Nack.</description>
					<bitRange>[10:10]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>ACKNOWLEDGED_THE_DA</name>
							<description>Acknowledged. The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>NOT_ACKNOWLEDGED_TH</name>
							<description>Not acknowledged. The data currently being provided by the monitor function was not acknowledged by any receiver.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:11]</bitRange>
					
				</field>
			</fields>
		</register>
	</registers>
		</peripheral>
		<peripheral>
	<name>SPI0</name>
	<description>SPI</description>
	<groupName>SPI</groupName>
	<baseAddress>0x40058000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<interrupt>
	<name>SPI0</name>
	<value>0</value>
	</interrupt>
	<registers>
		<register>
			<name>CFG</name>
			<description>SPI Configuration register</description>
			<addressOffset>0x000</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>Enable</name>
					<description>SPI enable.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_THE_SPI_IS</name>
							<description>Disabled. The SPI is disabled and the internal state machine and counters are reset.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_THE_SPI_IS_</name>
							<description>Enabled. The SPI is enabled for operation.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[1:1]</bitRange>
			
				</field>
				<field>
					<name>Master</name>
					<description>Master mode select.</description>
					<bitRange>[2:2]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SLAVE_MODE_THE_SPI_</name>
							<description>Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>MASTER_MODE_THE_SPI</name>
							<description>Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>LSBF</name>
					<description>LSB First mode enable.</description>
					<bitRange>[3:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>STANDARD_DATA_IS_TR</name>
							<description>Standard. Data is transmitted and received in standard MSB first order.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REVERSE_DATA_IS_TRA</name>
							<description>Reverse. Data is transmitted and received in reverse order (LSB first).</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CPHA</name>
					<description>Clock Phase select. .</description>
					<bitRange>[4:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CHANGE_THE_SPI_CAPT</name>
							<description>Change. The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CAPTURE_THE_SPI_CHA</name>
							<description>Capture. The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CPOL</name>
					<description>Clock Polarity select.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>LOW_THE_REST_STATE_</name>
							<description>Low. The rest state of the clock (between frames) is low.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_THE_REST_STATE</name>
							<description>High. The rest state of the clock (between frames) is high.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[6:6]</bitRange>
			
				</field>
				<field>
					<name>Loop</name>
					<description>Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.</description>
					<bitRange>[7:7]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_</name>
							<description>Disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_</name>
							<description>Enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SPOL</name>
					<description>SSEL Polarity select.</description>
					<bitRange>[8:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>LOW_THE_SSEL_PIN_IS</name>
							<description>Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is not inverted relative to the pins.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_THE_SSEL_PIN_I</name>
							<description>High. The SSEL pin is active high. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:9]</bitRange>
			
				</field>
			</fields>
		</register>
		<register>
			<name>DLY</name>
			<description>SPI Delay register</description>
			<addressOffset>0x004</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>PRE_DELAY</name>
					<description>Controls the amount of time between SSEL assertion and the beginning of a data frame.  There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.</description>
					<bitRange>[3:0]</bitRange>
				</field>
				<field>
					<name>POST_DELAY</name>
					<description>Controls the amount of time between the end of a data frame and SSEL deassertion.  0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.</description>
					<bitRange>[7:4]</bitRange>
				</field>
				<field>
					<name>FRAME_DELAY</name>
					<description>Controls the minimum amount of time between adjacent data frames.  0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.</description>
					<bitRange>[11:8]</bitRange>
				</field>
				<field>
					<name>TRANSFER_DELAY</name>
					<description>Controls the minimum amount of time that the SSELs are deasserted between transfers.  0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.</description>
					<bitRange>[15:12]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>STAT</name>
			<description>SPI Status. Some status flags can be cleared by writing a 1 to that bit position</description>
			<addressOffset>0x008</addressOffset>
			<access>read-write</access>
			<resetValue>0x0102</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RXRDY</name>
					<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.</description>
					<bitRange>[0:0]</bitRange>
				</field>
				<field>
					<name>TXRDY</name>
					<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.</description>
					<bitRange>[1:1]</bitRange>
				</field>
				<field>
					<name>RXOV</name>
					<description>Receiver Overrun interrupt flag. This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.</description>
					<bitRange>[2:2]</bitRange>
				</field>
				<field>
					<name>TXUR</name>
					<description>Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TxUr flag is set. Data transmitted by the SPI should be considered undefined if TxUr is set.</description>
					<bitRange>[3:3]</bitRange>
				</field>
				<field>
					<name>SSA</name>
					<description>Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.</description>
					<bitRange>[4:4]</bitRange>
				</field>
				<field>
					<name>SSD</name>
					<description>Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.</description>
					<bitRange>[5:5]</bitRange>
				</field>
				<field>
					<name>STALLED</name>
					<description>Stalled status flag. This indicates whether the SPI is currently in a stall condition.</description>
					<bitRange>[6:6]</bitRange>
				</field>
				<field>
					<name>ENDTRANSFER</name>
					<description>End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes Idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted.</description>
					<bitRange>[7:7]</bitRange>
				</field>
				<field>
					<name>IDLE</name>
					<description>Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.</description>
					<bitRange>[8:8]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:9]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>INTENSET</name>
			<description>SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
			<addressOffset>0x00C</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RXRDYEN</name>
					<description>Determines whether an interrupt occurs when receiver data is available.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_INTERRUPT_WILL_BE</name>
							<description>No interrupt will be generated when receiver data is available.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>AN_INTERRUPT_WILL_BE</name>
							<description>An interrupt will be generated when receiver data is available in the RXDAT register.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>TXRDYEN</name>
					<description>Determines whether an interrupt occurs when the transmitter holding register is available.</description>
					<bitRange>[1:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_INTERRUPT_WILL_BE</name>
							<description>No interrupt will be generated when the transmitter holding register is available.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>AN_INTERRUPT_WILL_BE</name>
							<description>An interrupt will be generated when data may be written to TXDAT.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RXOVEN</name>
					<description>Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.</description>
					<bitRange>[2:2]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_INTERRUPT_WILL_BE</name>
							<description>No interrupt will be generated when a receiver overrun occurs.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>AN_INTERRUPT_WILL_BE</name>
							<description>An interrupt will be generated if a receiver overrun occurs.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>TXUREN</name>
					<description>Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.</description>
					<bitRange>[3:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_INTERRUPT_WILL_BE</name>
							<description>No interrupt will be generated when the transmitter underruns.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>AN_INTERRUPT_WILL_BE</name>
							<description>An interrupt will be generated if the transmitter underruns.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SSAEN</name>
					<description>Determines whether an interrupt occurs when one or more Slave Select is asserted.</description>
					<bitRange>[4:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_INTERRUPT_WILL_BE</name>
							<description>No interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>AN_INTERRUPT_WILL_BE</name>
							<description>An interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SSDEN</name>
					<description>Determines whether an interrupt occurs when all Slave Selects are deasserted.</description>
					<bitRange>[5:5]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_INTERRUPT_WILL_BE</name>
							<description>No interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>AN_INTERRUPT_WILL_BE</name>
							<description>An interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:6]</bitRange>
			
				</field>
			</fields>
		</register>
		<register>
			<name>INTENCLR</name>
			<description>SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.</description>
			<addressOffset>0x010</addressOffset>
			<access>write-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<fields>
				<field>
					<name>RXRDYEN</name>
					<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
					<bitRange>[0:0]</bitRange>
				</field>
				<field>
					<name>TXRDYEN</name>
					<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
					<bitRange>[1:1]</bitRange>
				</field>
				<field>
					<name>RXOVEN</name>
					<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
					<bitRange>[2:2]</bitRange>
				</field>
				<field>
					<name>TXUREN</name>
					<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
					<bitRange>[3:3]</bitRange>
				</field>
				<field>
					<name>SSAEN</name>
					<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
					<bitRange>[4:4]</bitRange>
				</field>
				<field>
					<name>SSDEN</name>
					<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
					<bitRange>[5:5]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>RXDAT</name>
			<description>SPI Receive Data</description>
			<addressOffset>0x014</addressOffset>
			<access>read-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<readAction>modify</readAction>
			<fields>
				<field>
					<name>RXDAT</name>
					<description>Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the FLen setting in TXCTL / TXDATCTL.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>RXSSELN</name>
					<description>Slave Select for receive. This field allows the state of the  SSEL pin to be saved along with received data. The value will reflect the SSEL pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
					<bitRange>[16:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[19:17]</bitRange>
				</field>
				<field>
					<name>SOT</name>
					<description>Start of Transfer flag. This flag will be 1 if this is the first frame after SSEL went from  deasserted to  asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the frame length is greater than 16 bit.</description>
					<bitRange>[20:20]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved, the value read from a reserved bit is not defined.</description>
					<bitRange>[31:21]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>TXDATCTL</name>
			<description>SPI Transmit Data with Control</description>
			<addressOffset>0x018</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>TXDAT</name>
					<description>Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.</description>
					<bitRange>[15:0]</bitRange>
			
				</field>
				<field>
					<name>TXSSELN</name>
					<description>Transmit Slave Select . This field controls what is output for SSEL in master mode.  The active state of the SSEL function is configured by bits in the CFG register.</description>
					<bitRange>[16:16]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SSEL_ASSERTED_</name>
							<description>SSEL  asserted.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SSEL_NOT_ASSERTED_</name>
							<description>SSEL not asserted.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[19:17]</bitRange>
			
				</field>
				<field>
					<name>EOT</name>
					<description>End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.</description>
					<bitRange>[20:20]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SSEL_NOT_DEASSERTED_</name>
							<description>SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SSEL_DEASSERTED_THI</name>
							<description>SSEL deasserted. This piece of data is treated as the end of a transfer. SSELs will be deasserted at the end of this piece of data.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>EOF</name>
					<description>End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.</description>
					<bitRange>[21:21]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DATA_NOT_EOF_THIS_P</name>
							<description>Data not EOF. This piece of data transmitted is not treated as the end of a frame.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>DATA_EOF_THIS_PIECE</name>
							<description>Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RXIGNORE</name>
					<description>Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process.</description>
					<bitRange>[22:22]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>READ_RECEIVED_DATA_</name>
							<description>Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>IGNORE_RECEIVED_DATA</name>
							<description>Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[23:23]</bitRange>
			
				</field>
				<field>
					<name>FLEN</name>
					<description>Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by multiple sequential frames Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 1 bit in length. 0x2 = Data frame is 3 bits in length. ... 0xF = Data frame is 16 bits in length.</description>
					<bitRange>[27:24]</bitRange>
			
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:28]</bitRange>
			
				</field>
			</fields>
		</register>
		<register>
			<name>TXDAT</name>
			<description>SPI Transmit Data</description>
			<addressOffset>0x01C</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>DATA</name>
					<description>Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Only zero should be written.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>TXCTL</name>
			<description>SPI Transmit Control</description>
			<addressOffset>0x020</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>TX_SSEL</name>
					<description>Transmit Slave Select.</description>
					<bitRange>[16:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[19:17]</bitRange>
				</field>
				<field>
					<name>EOT</name>
					<description>End of Transfer.</description>
					<bitRange>[20:20]</bitRange>
				</field>
				<field>
					<name>EOF</name>
					<description>End of Frame.</description>
					<bitRange>[21:21]</bitRange>
				</field>
				<field>
					<name>RXIGNORE</name>
					<description>Receive Ignore.</description>
					<bitRange>[22:22]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[23:23]</bitRange>
				</field>
				<field>
					<name>FLEN</name>
					<description>Frame Length.</description>
					<bitRange>[27:24]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:28]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>DIV</name>
			<description>SPI clock Divider</description>
			<addressOffset>0x024</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>DIVVAL</name>
					<description>Rate divider value -1. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode.  DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, etc. the maximum possible divide is for the value 0xFFFF, which results in PCLK/65536.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>INTSTAT</name>
			<description>SPI Interrupt Status</description>
			<addressOffset>0x028</addressOffset>
			<access>read-only</access>
			<resetValue>0x02</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RXRDY</name>
					<description>Receiver Ready flag.</description>
					<bitRange>[0:0]</bitRange>
				</field>
				<field>
					<name>TXRDY</name>
					<description>Transmitter Ready flag.</description>
					<bitRange>[1:1]</bitRange>
				</field>
				<field>
					<name>RXOV</name>
					<description>Receiver Overrun interrupt flag.</description>
					<bitRange>[2:2]</bitRange>
				</field>
				<field>
					<name>TXUR</name>
					<description>Transmitter Underrun interrupt flag.</description>
					<bitRange>[3:3]</bitRange>
				</field>
				<field>
					<name>SSA</name>
					<description>Slave Select Assert.</description>
					<bitRange>[4:4]</bitRange>
				</field>
				<field>
					<name>SSD</name>
					<description>Slave Select Deassert.</description>
					<bitRange>[5:5]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Read value is undefined, only zero should be written.</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
	</registers>
		</peripheral>
		<peripheral derivedFrom="SPI0">
			<name>SPI1</name>
			<baseAddress>0x4005C000</baseAddress>
			<addressBlock>
				<offset>0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>SPI1</name>
				<value>1</value>
			</interrupt>
		</peripheral>


		
		<peripheral>
	<name>USART0</name>
	<description>USART</description>
	<groupName>USART</groupName>
	<baseAddress>0x40064000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<interrupt>
	<name>UART0</name>
	<value>3</value>
	</interrupt>
	<registers>						
	<register>					
		<name>CFG</name>				
		<description>USART Configuration register. Basic USART configuration settings that typically are not changed during operation.</description>				
		<addressOffset>0x000</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>ENABLE</name>		
				<description>USART Enable.</description>		
				<bitRange>[0:0]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>DISABLED_THE_USART_</name>
						<description>Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts  are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt if  enabled because the transmitter has been reset and is therefore available.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ENABLED_THE_USART_I</name>
						<description>Enabled. The USART is enabled for operation.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[1:1]</bitRange>		
					
			</field>			
			<field>			
				<name>DATALEN</name>		
				<description>Selects the data size for the USART.</description>		
				<bitRange>[3:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>7_BIT_DATA_LENGTH_</name>
						<description>7 bit Data length.</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>8_BIT_DATA_LENGTH_</name>
						<description>8 bit Data length.</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>9_BIT_DATA_LENGTH_T</name>
						<description>9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTRL register.</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RESERVED_</name>
						<description>Reserved.</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>PARITYSEL</name>		
				<description>Selects what type of parity is used by the USART.</description>		
				<bitRange>[5:4]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_PARITY_</name>
						<description>No parity.</description>
						<value>0x0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RESERVED_</name>
						<description>Reserved.</description>
						<value>0x1</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>EVEN_PARITY_ADDS_A_</name>
						<description>Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.</description>
						<value>0x2</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>ODD_PARITY_ADDS_A_B</name>
						<description>Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.</description>
						<value>0x3</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>STOPLEN</name>		
				<description>Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>1_STOP_BIT_</name>
						<description>1 stop bit.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>2_STOP_BITS_THIS_SE</name>
						<description>2 stop bits. This setting should only be used for asynchronous communication.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Only write 0 to this bit.</description>		
				<bitRange>[7:7]</bitRange>		
					
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[8:8]</bitRange>		
					
			</field>			
			<field>			
				<name>CTSEN</name>		
				<description>CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 16.7.3 for more information.</description>		
				<bitRange>[9:9]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_FLOW_CONTROL_THE</name>
						<description>No flow control. The transmitter does not receive any automatic flow control signal.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>FLOW_CONTROL_ENABLED</name>
						<description>Flow control enabled. The transmitter uses external or internal CTS for flow control purposes.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[10:10]</bitRange>		
					
			</field>			
			<field>			
				<name>SYNCEN</name>		
				<description>Selects synchronous or asynchronous operation.</description>		
				<bitRange>[11:11]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ASYNCHRONOUS_MODE_IS</name>
						<description>Asynchronous mode is selected.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>SYNCHRONOUS_MODE_IS_</name>
						<description>Synchronous mode is selected.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>CLKPOL</name>		
				<description>Selects the clock polarity and sampling edge of received data in synchronous mode.</description>		
				<bitRange>[12:12]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>FALLING_EDGE_UN_RXD</name>
						<description>Falling edge. Un_RXD is sampled on the falling edge of SCLK.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>RISING_EDGE_UN_RXD_</name>
						<description>Rising edge. Un_RXD is sampled on the rising edge of SCLK.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[13:13]</bitRange>		
					
			</field>			
			<field>			
				<name>SYNCMST</name>		
				<description>Synchronous mode Master select.</description>		
				<bitRange>[14:14]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>SLAVE_WHEN_SYNCHRON</name>
						<description>Slave. When synchronous mode is enabled, the USART is a slave.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>MASTER_WHEN_SYNCHRO</name>
						<description>Master. When synchronous mode is enabled, the USART is a master. In asynchronous mode, the baud rate clock will be output on SCLK if it is connected to a pin.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>LOOP</name>		
				<description>Selects data loopback mode.</description>		
				<bitRange>[15:15]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NORMAL_OPERATION_</name>
						<description>Normal operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>LOOPBACK_MODE_THIS_</name>
						<description>Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:16]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>CTRL</name>				
		<description>USART Control register. USART control settings that are more likely to change during operation.</description>				
		<addressOffset>0x004</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[0:0]</bitRange>		
					
			</field>			
			<field>			
				<name>TXBRKEN</name>		
				<description>Break Enable.</description>		
				<bitRange>[1:1]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NORMAL_OPERATION_</name>
						<description>Normal operation.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CONTINUOUS_BREAK_IS_</name>
						<description>Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTRL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>ADDRDET</name>		
				<description>Enable address detect mode.</description>		
				<bitRange>[2:2]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>ENABLED_THE_USART_R</name>
						<description>Enabled. The USART receiver is enabled for all incoming data.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLED_THE_USART_</name>
						<description>Disabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[5:3]</bitRange>		
					
			</field>			
			<field>			
				<name>TXDIS</name>		
				<description>Transmit Disable.</description>		
				<bitRange>[6:6]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NOT_DISABLED_USART_</name>
						<description>Not disabled. USART transmitter is not disabled.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>DISABLED_USART_TRAN</name>
						<description>Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[7:7]</bitRange>		
					
			</field>			
			<field>			
				<name>CC</name>		
				<description>Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.</description>		
				<bitRange>[8:8]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>CLOCK_ON_CHARACTER_</name>
						<description>Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>CONTINUOUS_CLOCK_SC</name>
						<description>Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>CLRCC</name>		
				<description>Clear Continuous Clock.</description>		
				<bitRange>[9:9]</bitRange>		
				<enumeratedValues>		
				<name>ENUM</name>		
					<enumeratedValue>	
						<name>NO_AFFECT_ON_THE_CC_</name>
						<description>No affect on the CC bit.</description>
						<value>0</value>
					</enumeratedValue>	
					<enumeratedValue>	
						<name>AUTO_CLEAR_THE_CC_B</name>
						<description>Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.</description>
						<value>1</value>
					</enumeratedValue>	
				</enumeratedValues>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:10]</bitRange>		
					
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>STAT</name>				
		<description>USART Status register. The complete status value can be read here. Writing 1s clears some bits in the register. Some bits can be cleared by writing a 1 to them.</description>				
		<addressOffset>0x008</addressOffset>				
		<access>read-write</access>				
		<resetValue>0x000E</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>RXRDY</name>		
				<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDATA or RXDATASTAT registers.</description>		
				<bitRange>[0:0]</bitRange>		
			</field>			
			<field>			
				<name>RXIDLE</name>		
				<description>Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.</description>		
				<bitRange>[1:1]</bitRange>		
			</field>			
			<field>			
				<name>TXRDY</name>		
				<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDATA until the data is moved to the transmit shift register.</description>		
				<bitRange>[2:2]</bitRange>		
			</field>			
			<field>			
				<name>TXIDLE</name>		
				<description>Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.</description>		
				<bitRange>[3:3]</bitRange>		
			</field>			
			<field>			
				<name>CTS</name>		
				<description>This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.</description>		
				<bitRange>[4:4]</bitRange>		
			</field>			
			<field>			
				<name>DELTACTS</name>		
				<description>This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.</description>		
				<bitRange>[5:5]</bitRange>		
			</field>			
			<field>			
				<name>TXDISINT</name>		
				<description>Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1).</description>		
				<bitRange>[6:6]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[7:7]</bitRange>		
			</field>			
			<field>			
				<name>OVERRUNINT</name>		
				<description>Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.</description>		
				<bitRange>[8:8]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[9:9]</bitRange>		
			</field>			
			<field>			
				<name>RXBRK</name>		
				<description>Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.</description>		
				<bitRange>[10:10]</bitRange>		
			</field>			
			<field>			
				<name>DELTARXBRK</name>		
				<description>This bit is set when a change in the state of receiver break detection occurs. Cleared by software.</description>		
				<bitRange>[11:11]</bitRange>		
			</field>			
			<field>			
				<name>START</name>		
				<description>This bit is set when a start is detected on the receiver input and subsequently confirmed by a mid-bit sample. Its purpose is primarily to allow wakeup from Power-down mode immediately when a start is detected. Cleared by software.</description>		
				<bitRange>[12:12]</bitRange>		
			</field>			
			<field>			
				<name>FRAMERRINT</name>		
				<description>Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>		
				<bitRange>[13:13]</bitRange>		
			</field>			
			<field>			
				<name>PARITYERRINT</name>		
				<description>Parity Error interrupt flag. This flag is set when a parity error is detected in a received character, if parity is enabled via the Parity field in the CFG register.</description>		
				<bitRange>[14:14]</bitRange>		
			</field>			
			<field>			
				<name>RXNOISEINT</name>		
				<description>Received Noise interrupt flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. The Noise bit is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. RXNOISEINT is not updated during a received break.</description>		
				<bitRange>[15:15]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:16]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>INTENSET</name>				
		<description>Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>				
		<addressOffset>0x00C</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>RXRDYEN</name>		
				<description>When 1, enables an interrupt when there is a received character available to be read from the RXDATA register.</description>		
				<bitRange>[0:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[1:1]</bitRange>		
			</field>			
			<field>			
				<name>TXRDYEN</name>		
				<description>When 1, enables an interrupt when the TXDATA register is available to take another character to transmit.</description>		
				<bitRange>[2:2]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[4:3]</bitRange>		
			</field>			
			<field>			
				<name>DELTACTSEN</name>		
				<description>When 1, enables an interrupt when there is a change in the state of the CTS input.</description>		
				<bitRange>[5:5]</bitRange>		
			</field>			
			<field>			
				<name>TXDISINTEN</name>		
				<description>When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.</description>		
				<bitRange>[6:6]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[7:7]</bitRange>		
			</field>			
			<field>			
				<name>OVERRUNEN</name>		
				<description>When 1, enables an interrupt when an overrun error occurred.</description>		
				<bitRange>[8:8]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[10:9]</bitRange>		
			</field>			
			<field>			
				<name>DELTARXBRKEN</name>		
				<description>When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).</description>		
				<bitRange>[11:11]</bitRange>		
			</field>			
			<field>			
				<name>STARTEN</name>		
				<description>When 1, enables an interrupt when a received start bit has been detected.</description>		
				<bitRange>[12:12]</bitRange>		
			</field>			
			<field>			
				<name>FRAMERREN</name>		
				<description>When 1, enables an interrupt when a framing error has been detected.</description>		
				<bitRange>[13:13]</bitRange>		
			</field>			
			<field>			
				<name>PARITYERREN</name>		
				<description>When 1, enables an interrupt when a parity error has been detected.</description>		
				<bitRange>[14:14]</bitRange>		
			</field>			
			<field>			
				<name>RXNOISEEN</name>		
				<description>When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 164.</description>		
				<bitRange>[15:15]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:16]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>INTENCLR</name>				
		<description>Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.</description>				
		<addressOffset>0x010</addressOffset>				
		<access>write-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0x00000000</resetMask>				
		<fields>				
			<field>			
				<name>RXRDYCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[0:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[1:1]</bitRange>		
			</field>			
			<field>			
				<name>TXRDYCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[2:2]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[4:3]</bitRange>		
			</field>			
			<field>			
				<name>DELTACTSCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[5:5]</bitRange>		
			</field>			
			<field>			
				<name>TXDISINTCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[6:6]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[7:7]</bitRange>		
			</field>			
			<field>			
				<name>OVERRUNCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[8:8]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[10:9]</bitRange>		
			</field>			
			<field>			
				<name>DELTARXBRKCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[11:11]</bitRange>		
			</field>			
			<field>			
				<name>STARTCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[12:12]</bitRange>		
			</field>			
			<field>			
				<name>FRAMERRCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[13:13]</bitRange>		
			</field>			
			<field>			
				<name>PARITYERRCLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[14:14]</bitRange>		
			</field>			
			<field>			
				<name>RXNOISECLR</name>		
				<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>		
				<bitRange>[15:15]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:16]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>RXDATA</name>				
		<description>Receiver Data register. Contains the last character received.</description>				
		<addressOffset>0x014</addressOffset>				
		<access>read-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0x00000000</resetMask>
		<readAction>modify</readAction>
		<fields>				
			<field>			
				<name>RXDAT</name>		
				<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>		
				<bitRange>[8:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved, the value read from a reserved bit is not defined.</description>		
				<bitRange>[31:9]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>RXDATASTAT</name>				
		<description>Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows software to recover incoming data and status together.</description>				
		<addressOffset>0x018</addressOffset>				
		<access>read-only</access>				
		<resetValue>0</resetValue>				
		<resetMask>0x00000000</resetMask>		
        <readAction>modify</readAction>		
		<fields>				
			<field>			
				<name>RXDAT</name>		
				<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>		
				<bitRange>[8:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved, the value read from a reserved bit is not defined.</description>		
				<bitRange>[12:9]</bitRange>		
			</field>			
			<field>			
				<name>FRAMERR</name>		
				<description>Framing Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>		
				<bitRange>[13:13]</bitRange>		
			</field>			
			<field>			
				<name>PARITYERR</name>		
				<description>Parity Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.</description>		
				<bitRange>[14:14]</bitRange>		
			</field>			
			<field>			
				<name>RXNOISE</name>		
				<description>Received Noise flag. See description of the RxNoiseInt bit in Table 164.</description>		
				<bitRange>[15:15]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved, the value read from a reserved bit is not defined.</description>		
				<bitRange>[31:16]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>TXDATA</name>				
		<description>Transmit Data register. Data to be transmitted is written here.</description>				
		<addressOffset>0x01C</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>TXDAT</name>		
				<description>Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available.</description>		
				<bitRange>[8:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Only zero should be written.</description>		
				<bitRange>[31:9]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>BRG</name>				
		<description>Baud Rate Generator register. 16-bit integer baud rate divisor value.</description>				
		<addressOffset>0x020</addressOffset>				
		<access>read-write</access>				
		<resetValue>0</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>BRGVAL</name>		
				<description>This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.</description>		
				<bitRange>[15:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:16]</bitRange>		
			</field>			
		</fields>				
	</register>					
	<register>					
		<name>INTSTAT</name>				
		<description>Interrupt status register. Reflects interrupts that are currently enabled.</description>				
		<addressOffset>0x024</addressOffset>				
		<access>read-only</access>				
		<resetValue>0x0005</resetValue>				
		<resetMask>0xFFFFFFFF</resetMask>				
		<fields>				
			<field>			
				<name>RXRDY</name>		
				<description>Receiver Ready flag.</description>		
				<bitRange>[0:0]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[1:1]</bitRange>		
			</field>			
			<field>			
				<name>TXRDY</name>		
				<description>Transmitter Ready flag.</description>		
				<bitRange>[2:2]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[4:3]</bitRange>		
			</field>			
			<field>			
				<name>DELTACTS</name>		
				<description>This bit is set when a change in the state of the CTS input is detected.</description>		
				<bitRange>[5:5]</bitRange>		
			</field>			
			<field>			
				<name>TXDISINT</name>		
				<description>Transmitter Disabled Interrupt flag.</description>		
				<bitRange>[6:6]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[7:7]</bitRange>		
			</field>			
			<field>			
				<name>OVERRUNINT</name>		
				<description>Overrun Error interrupt flag.</description>		
				<bitRange>[8:8]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[10:9]</bitRange>		
			</field>			
			<field>			
				<name>DELTARXBRK</name>		
				<description>This bit is set when a change in the state of receiver break detection occurs.</description>		
				<bitRange>[11:11]</bitRange>		
			</field>			
			<field>			
				<name>START</name>		
				<description>This bit is set when a start is detected on the receiver input.</description>		
				<bitRange>[12:12]</bitRange>		
			</field>			
			<field>			
				<name>FRAMERRINT</name>		
				<description>Framing Error interrupt flag.</description>		
				<bitRange>[13:13]</bitRange>		
			</field>			
			<field>			
				<name>PARITYERRINT</name>		
				<description>Parity Error interrupt flag.</description>		
				<bitRange>[14:14]</bitRange>		
			</field>			
			<field>			
				<name>RXNOISEINT</name>		
				<description>Received Noise interrupt flag.</description>		
				<bitRange>[15:15]</bitRange>		
			</field>			
			<field>			
				<name>RESERVED</name>		
				<description>Reserved. Read value is undefined, only zero should be written.</description>		
				<bitRange>[31:16]</bitRange>		
			</field>			
		</fields>				
	</register>					
</registers>						

		</peripheral>
		<peripheral derivedFrom="USART0">
			<name>USART1</name>
			<baseAddress>0x40068000</baseAddress>
			<addressBlock>
				<offset>0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>UART1</name>
				<value>4</value>
			</interrupt>
		</peripheral>
		<peripheral derivedFrom="USART0">
			<name>USART2</name>
			<baseAddress>0x4006C000</baseAddress>
			<addressBlock>
				<offset>0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<interrupt>
				<name>UART2</name>
				<value>5</value>
			</interrupt>
		</peripheral>

		<peripheral>
			<name>CRC</name>
			<description>Cyclic Redundancy Check (CRC) engine</description>
			<groupName>CRC</groupName>
			<baseAddress>0x50000000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<registers>
				<register>
					<name>MODE</name>
					<description>CRC mode register</description>
					<addressOffset>0x00</addressOffset>
					<access>read-write</access>
					<resetValue>0x00000000</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>CRC_POLY</name>
							<description>CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial</description>
							<bitRange>[1:0]</bitRange>
						</field>
						<field>
							<name>BIT_RVS_WR</name>
							<description>Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)</description>
							<bitRange>[2:2]</bitRange>
						</field>
						<field>
							<name>CMPL_WR</name>
							<description>Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA</description>
							<bitRange>[3:3]</bitRange>
						</field>
						<field>
							<name>BIT_RVS_SUM</name>
							<description>CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM</description>
							<bitRange>[4:4]</bitRange>
						</field>
						<field>
							<name>CMPL_SUM</name>
							<description>CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM</description>
							<bitRange>[5:5]</bitRange>
						</field>
						<field>
							<name>Reserved</name>
							<description>Always 0 when read</description>
							<bitRange>[31:6]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>SEED</name>
					<description>CRC seed register</description>
					<addressOffset>0x04</addressOffset>
					<access>read-write</access>
					<resetValue>0x0000FFFF</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>CRC_SEED</name>
							<description>A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.</description>
							<bitRange>[31:0]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>SUM</name>
					<description>CRC checksum register</description>
					<addressOffset>0x08</addressOffset>
					<access>read-only</access>
					<resetValue>0x0000FFFF</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>CRC_SUM</name>
							<description>The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.</description>
							<bitRange>[31:0]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>WR_DATA</name>
					<description>CRC data register</description>
					<alternateRegister>SUM</alternateRegister>
					<addressOffset>0x08</addressOffset>
					<access>write-only</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>CRC_WR_DATA</name>
							<description>Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.</description>
							<bitRange>[31:0]</bitRange>
						</field>
					</fields>
				</register>
			</registers>
		</peripheral>
		
		<peripheral>
	<name>SCT</name>
	<description>State Configurable Timer (SCT)</description>
	<groupName>SCT</groupName>
	<baseAddress>0x50004000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<interrupt>
	<name>SCT</name>
	<value>9</value>
	</interrupt>
	<registers>
		<register>
			<name>CONFIG</name>
			<description>SCT configuration register</description>
			<addressOffset>0x000</addressOffset>
			<access>read-write</access>
			<resetValue>0x00007E00</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>UNIFY</name>
					<description>SCT operation</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>THE_SCT_OPERATES_AS_</name>
							<description>The SCT operates as two 16-bit counters named L and H.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>UNIFIED</name>
							<description>The SCT operates as a unified 32-bit counter.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLKMODE</name>
					<description>SCT clock mode</description>
					<bitRange>[2:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>THE_BUS_CLOCK_CLOCKS</name>
							<description>The bus clock clocks the SCT and prescalers.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_SCT_CLOCK_IS_THE</name>
							<description>The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_INPUT_SELECTED_B</name>
							<description>The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RESERVED_</name>
							<description>Reserved.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CLKSEL</name>
					<description>SCT clock select</description>
					<bitRange>[6:3]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>RISING_EDGES_ON_INPUT_0</name>
							<description>Rising edges on input 0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGES_ON_INPUT_0</name>
							<description>Falling edges on input 0.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGES_ON_INPUT_1</name>
							<description>Rising edges on input 1.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGES_ON_INPUT_1</name>
							<description>Falling edges on input 1.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGES_ON_INPUT_2</name>
							<description>Rising edges on input 2.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGES_ON_INPUT_2</name>
							<description>Falling edges on input 2.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGES_ON_INPUT_3</name>
							<description>Rising edges on input 3.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGES_ON_INPUT_3</name>
							<description>Falling edges on input 3.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>NORELAOD_L</name>
					<description>A 1 in this bit prevents the lower match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set.</description>
					<bitRange>[7:7]</bitRange>
				
				</field>
				<field>
					<name>NORELOAD_H</name>
					<description>A 1 in this bit prevents the higher match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set.</description>
					<bitRange>[8:8]</bitRange>
				
				</field>
				<field>
					<name>INSYNC</name>
					<description>Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used.</description>
					<bitRange>[16:9]</bitRange>
				
				</field>
				<field>
					<name>AUTOLIMIT_L</name>
					<description>A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set.</description>
					<bitRange>[17:17]</bitRange>
				
				</field>
				<field>
					<name>AUTOLIMIT_H</name>
					<description>A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set.</description>
					<bitRange>[18:18]</bitRange>
				
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:19]</bitRange>
				
				</field>
			</fields>
		</register>
		<register>
			<name>CTRL</name>
			<description>SCT control register</description>
			<addressOffset>0x004</addressOffset>
			<access>read-write</access>
			<resetValue>0x00040004</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>DOWN_L</name>
					<description>This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
					<bitRange>[0:0]</bitRange>
				
				</field>
				<field>
					<name>STOP_L</name>
					<description>When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes.</description>
					<bitRange>[1:1]</bitRange>
				
				</field>
				<field>
					<name>HALT_L</name>
					<description>When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.</description>
					<bitRange>[2:2]</bitRange>
				
				</field>
				<field>
					<name>CLRCTR_L</name>
					<description>Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.</description>
					<bitRange>[3:3]</bitRange>
				
				</field>
				<field>
					<name>BIDIR_L</name>
					<description>L or unified counter direction select</description>
					<bitRange>[4:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CLEAR_TO_ZERO</name>
							<description>The counter counts up to its limit condition, then is cleared to zero.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_COUNTER_COUNTS_U</name>
							<description>The counter counts up to its limit, then counts down to a limit condition or to 0.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>PRE_L</name>
					<description>Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value.</description>
					<bitRange>[12:5]</bitRange>
				
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[15:13]</bitRange>
				
				</field>
				<field>
					<name>DOWN_H</name>
					<description>This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
					<bitRange>[16:16]</bitRange>
				
				</field>
				<field>
					<name>STOP_H</name>
					<description>When this bit is 1 and HALT is 0, the H counter does not, run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes.</description>
					<bitRange>[17:17]</bitRange>
				
				</field>
				<field>
					<name>HALT_H</name>
					<description>When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.</description>
					<bitRange>[18:18]</bitRange>
				
				</field>
				<field>
					<name>CLRCTR_H</name>
					<description>Writing a 1 to this bit clears the H counter. This bit always reads as 0.</description>
					<bitRange>[19:19]</bitRange>
				
				</field>
				<field>
					<name>BIDIR_H</name>
					<description>Direction select</description>
					<bitRange>[20:20]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CLEAR_TO_ZERO</name>
							<description>The H counter counts up to its limit condition, then is cleared to zero.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>THE_H_COUNTER_COUNTS</name>
							<description>The H counter counts up to its limit, then counts down to a limit condition or to 0.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>PRE_H</name>
					<description>Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value.</description>
					<bitRange>[28:21]</bitRange>
				
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:29]</bitRange>
				
				</field>
			</fields>
		</register>
		<register>
			<name>LIMIT</name>
			<description>SCT limit register</description>
			<addressOffset>0x008</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>LIMMSK_L</name>
					<description>If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:6]</bitRange>
				</field>
				<field>
					<name>LIMMSK_H</name>
					<description>If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).</description>
					<bitRange>[20:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:21]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>HALT</name>
			<description>SCT halt condition register</description>
			<addressOffset>0x00C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>HALTMSK_L</name>
					<description>If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:6]</bitRange>
				</field>
				<field>
					<name>HALTMSK_H</name>
					<description>If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).</description>
					<bitRange>[20:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:21]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>STOP</name>
			<description>SCT stop condition register</description>
			<addressOffset>0x010</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STOPMSK_L</name>
					<description>If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:6]</bitRange>
				</field>
				<field>
					<name>STOPMSK_H</name>
					<description>If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).</description>
					<bitRange>[20:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:21]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>START</name>
			<description>SCT start condition register</description>
			<addressOffset>0x014</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STARTMSK_L</name>
					<description>If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:6]</bitRange>
				</field>
				<field>
					<name>STARTMSK_H</name>
					<description>If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).</description>
					<bitRange>[20:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:21]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>COUNT</name>
			<description>SCT counter register</description>
			<addressOffset>0x040</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CTR_L</name>
					<description>When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>CTR_H</name>
					<description>When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>STATE</name>
			<description>SCT state register</description>
			<addressOffset>0x044</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATE_L</name>
					<description>State variable.</description>
					<bitRange>[4:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:5]</bitRange>
				</field>
				<field>
					<name>STATE_H</name>
					<description>State variable.</description>
					<bitRange>[20:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:21]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>INPUT</name>
			<description>SCT input register</description>
			<addressOffset>0x048</addressOffset>
			<access>read-only</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>AIN0</name>
					<description>Real-time status of input 0.</description>
					<bitRange>[0:0]</bitRange>
				</field>
				<field>
					<name>AIN1</name>
					<description>Real-time status of input 1.</description>
					<bitRange>[1:1]</bitRange>
				</field>
				<field>
					<name>AIN2</name>
					<description>Real-time status of input 2.</description>
					<bitRange>[2:2]</bitRange>
				</field>
				<field>
					<name>AIN3</name>
					<description>Real-time status of input 3.</description>
					<bitRange>[3:3]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:4]</bitRange>
				</field>
				<field>
					<name>SIN0</name>
					<description>Input 0 state synchronized to the SCT clock.</description>
					<bitRange>[16:16]</bitRange>
				</field>
				<field>
					<name>SIN1</name>
					<description>Input 1 state synchronized to the SCT clock.</description>
					<bitRange>[17:17]</bitRange>
				</field>
				<field>
					<name>SIN2</name>
					<description>Input 2 state synchronized to the SCT clock.</description>
					<bitRange>[18:18]</bitRange>
				</field>
				<field>
					<name>SIN3</name>
					<description>Input 3 state synchronized to the SCT clock.</description>
					<bitRange>[19:19]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:20]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>REGMODE</name>
			<description>SCT match/capture registers mode register</description>
			<addressOffset>0x04C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>REGMOD_L</name>
					<description>Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4).  0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
					<bitRange>[4:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:5]</bitRange>
				</field>
				<field>
					<name>REGMOD_H</name>
					<description>Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 19). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
					<bitRange>[19:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:20]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>OUTPUT</name>
			<description>SCT output register</description>
			<addressOffset>0x050</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>OUT</name>
					<description>Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).</description>
					<bitRange>[3:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:4]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>OUTPUTDIRCTRL</name>
			<description>SCT output counter direction control register</description>
			<addressOffset>0x054</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SETCLR0</name>
					<description>Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.</description>
					<bitRange>[1:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SET_AND_CLEAR_DO_NOT</name>
							<description>Set and clear do not depend on any counter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_AND_CLEAR_ARE_RE</name>
							<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REVERSED_ON_H</name>
							<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
							<value>0x2</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SETCLR1</name>
					<description>Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.</description>
					<bitRange>[3:2]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SET_AND_CLEAR_DO_NOT</name>
							<description>Set and clear do not depend on any counter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_AND_CLEAR_ARE_RE</name>
							<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REVERSED_ON_H</name>
							<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
							<value>0x2</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SETCLR2</name>
					<description>Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.</description>
					<bitRange>[5:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SET_AND_CLEAR_DO_NOT</name>
							<description>Set and clear do not depend on any counter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_AND_CLEAR_ARE_RE</name>
							<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REVERSED_ON_H</name>
							<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
							<value>0x2</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SETCLR3</name>
					<description>Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.</description>
					<bitRange>[7:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>SET_AND_CLEAR_DO_NOT</name>
							<description>Set and clear do not depend on any counter.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_AND_CLEAR_ARE_RE</name>
							<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>REVERSED_ON_H</name>
							<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
							<value>0x2</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:8]</bitRange>
				
				</field>
			</fields>
		</register>
		<register>
			<name>RES</name>
			<description>SCT conflict resolution register</description>
			<addressOffset>0x058</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>O0RES</name>
					<description>Effect of simultaneous set and clear on output 0.</description>
					<bitRange>[1:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_CHANGE_</name>
							<description>No change.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_OUTPUT_OR_CLEAR</name>
							<description>Set output (or clear based on the SETCLR0 field).</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CLEAR_OUTPUT_OR_SET</name>
							<description>Clear output (or set based on the SETCLR0 field).</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>TOGGLE_OUTPUT_</name>
							<description>Toggle output.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>O1RES</name>
					<description>Effect of simultaneous set and clear on output 1.</description>
					<bitRange>[3:2]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_CHANGE_</name>
							<description>No change.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_OUTPUT_OR_CLEAR</name>
							<description>Set output (or clear based on the SETCLR1 field).</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CLEAR_OUTPUT_OR_SET</name>
							<description>Clear output (or set based on the SETCLR1 field).</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>TOGGLE_OUTPUT_</name>
							<description>Toggle output.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>O2RES</name>
					<description>Effect of simultaneous set and clear on output 2.</description>
					<bitRange>[5:4]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_CHANGE_</name>
							<description>No change.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_OUTPUT_OR_CLEAR</name>
							<description>Set output (or clear based on the SETCLR2 field).</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CLEAR_OUTPUT_N_OR_S</name>
							<description>Clear output n (or set based on the SETCLR2 field).</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>TOGGLE_OUTPUT_</name>
							<description>Toggle output.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>O3RES</name>
					<description>Effect of simultaneous set and clear on output 3.</description>
					<bitRange>[7:6]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>NO_CHANGE_</name>
							<description>No change.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>SET_OUTPUT_OR_CLEAR</name>
							<description>Set output (or clear based on the SETCLR3 field).</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CLEAR_OUTPUT_OR_SET</name>
							<description>Clear output (or set based on the SETCLR3 field).</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>TOGGLE_OUTPUT_</name>
							<description>Toggle output.</description>
							<value>0x3</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:8]</bitRange>
				
				</field>
			</fields>
		</register>
		<register>
			<name>EVEN</name>
			<description>SCT event enable register</description>
			<addressOffset>0x0F0</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>IEN</name>
					<description>The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>EVFLAG</name>
			<description>SCT event flag register</description>
			<addressOffset>0x0F4</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>FLAG</name>
					<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>CONEN</name>
			<description>SCT conflict enable register</description>
			<addressOffset>0x0F8</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>NCEN</name>
					<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).</description>
					<bitRange>[3:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:4]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>CONFLAG</name>
			<description>SCT conflict flag register</description>
			<addressOffset>0x0FC</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>NCFLAG</name>
					<description>Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).</description>
					<bitRange>[3:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[29:4]</bitRange>
				</field>
				<field>
					<name>BUSERRL</name>
					<description>The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful.</description>
					<bitRange>[30:30]</bitRange>
				</field>
				<field>
					<name>BUSERRH</name>
					<description>The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted.</description>
					<bitRange>[31:31]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<dim>5</dim>
			<dimIncrement>0x4</dimIncrement>
			<dimIndex>0-4</dimIndex>
			<name>MATCH%s</name>
			<description>SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0</description>
			<addressOffset>0x100</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>MATCHn_L</name>
					<description>When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>MATCHn_H</name>
					<description>When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<dim>5</dim>
			<dimIncrement>0x4</dimIncrement>
			<dimIndex>0-4</dimIndex>
			<name>CAP%s</name>
			<description>SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1</description>
			<alternateRegister>MATCH%s</alternateRegister>
			<addressOffset>0x100</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CAPn_L</name>
					<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>CAPn_H</name>
					<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<dim>5</dim>
			<dimIncrement>0x4</dimIncrement>
			<dimIndex>0-4</dimIndex>
			<name>MATCHREL%s</name>
			<description>SCT match reload value register 0 to 4 REGMOD0 = 0 to REGMODE4 = 0</description>
			<addressOffset>0x200</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RELOADn_L</name>
					<description>When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
					<bitRange>[15:0]</bitRange>
				</field>
				<field>
					<name>RELOADn_H</name>
					<description>When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
					<bitRange>[31:16]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<dim>5</dim>
			<dimIncrement>0x4</dimIncrement>
			<dimIndex>0-4</dimIndex>
			<name>CAPCTRL%s</name>
			<description>SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1</description>
			<alternateRegister>MATCHREL%s</alternateRegister>
			<addressOffset>0x200</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CAPCONm_L</name>
					<description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5).</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[15:6]</bitRange>
				</field>
				<field>
					<name>CAPCONm_H</name>
					<description>If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 20).</description>
					<bitRange>[20:16]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:17]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>EV0_STATE</name>
			<description>SCT event state register 0</description>
			<addressOffset>0x300</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATEMSKm</name>
					<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1).</description>
					<bitRange>[1:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:2]</bitRange>
				</field>
			</fields>
		</register>
		<register>							
								
			<name>EV0_CTRL</name>						
			<description>SCT event control register 0</description>						
			<addressOffset>0x304</addressOffset>						
			<access>read-write</access>						
			<resetValue>0x00000000</resetValue>						
			<resetMask>0xFFFFFFFF</resetMask>						
			<fields>						
				<field>					
					<name>MATCHSEL</name>				
					<description>Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running.</description>				
					<bitRange>[3:0]</bitRange>				
								
				</field>					
				<field>					
					<name>HEVENT</name>				
					<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>				
					<bitRange>[4:4]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_L_STATE_</name>		
							<description>Selects the L state and the L match register selected by MATCHSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_H_STATE_</name>		
							<description>Selects the H state and the H match register selected by MATCHSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>OUTSEL</name>				
					<description>Input/output select</description>				
					<bitRange>[5:5]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_INPUTS_E</name>		
							<description>Selects the inputs elected by IOSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_OUTPUTS_</name>		
							<description>Selects the outputs selected by IOSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>IOSEL</name>				
					<description>Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event.</description>				
					<bitRange>[9:6]</bitRange>				
									
				</field>					
				<field>					
					<name>IOCOND</name>				
					<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .</description>				
					<bitRange>[11:10]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>LOW</name>		
							<description>LOW</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>RISE</name>		
							<description>Rise</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>FALL</name>		
							<description>Fall</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>HIGH</name>		
							<description>HIGH</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>COMBMODE</name>				
					<description>Selects how the specified match and I/O condition are used and combined.</description>				
					<bitRange>[13:12]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>OR_THE_EVENT_OCCURS</name>		
							<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>MATCH_USES_THE_SPEC</name>		
							<description>MATCH. Uses the specified match only.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>IO_USES_THE_SPECIFI</name>		
							<description>IO. Uses the specified I/O condition only.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>AND_THE_EVENT_OCCUR</name>		
							<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATELD</name>				
					<description>This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.</description>				
					<bitRange>[14:14]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_ADDE</name>		
							<description>STATEV value is added into STATE (the carry-out is ignored).</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_LOAD</name>		
							<description>STATEV value is loaded into STATE.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATEV</name>				
					<description>This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value.</description>				
					<bitRange>[19:15]</bitRange>				
							
				</field>					
				<field>					
					<name>MATCHMEM</name>				
					<description>If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value.</description>				
					<bitRange>[20:20]</bitRange>				
						
				</field>					
				<field>					
					<name>DIRECTION</name>				
					<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>				
					<bitRange>[22:21]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>DIRECTION_INDEPENDEN</name>		
							<description>Direction independent. This event is triggered regardless of the count direction.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_UP_THIS_EV</name>		
							<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_DOWN_THIS_</name>		
							<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>RESERVED</name>				
					<description>Reserved</description>				
					<bitRange>[31:23]</bitRange>				
							
				</field>					
			</fields>						
		</register>							
		<register>
			
			<name>EV1_STATE</name>
			<description>SCT event state register 1</description>
			<addressOffset>0x308</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATEMSKm</name>
					<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1).</description>
					<bitRange>[1:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:2]</bitRange>
				</field>
			</fields>
		</register>
		<register>							
			
			<name>EV1_CTRL</name>						
			<description>SCT event control register 1</description>						
			<addressOffset>0x30C</addressOffset>						
			<access>read-write</access>						
			<resetValue>0x00000000</resetValue>						
			<resetMask>0xFFFFFFFF</resetMask>						
			<fields>						
				<field>					
					<name>MATCHSEL</name>				
					<description>Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running.</description>				
					<bitRange>[3:0]</bitRange>				
					
				</field>					
				<field>					
					<name>HEVENT</name>				
					<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>				
					<bitRange>[4:4]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_L_STATE_</name>		
							<description>Selects the L state and the L match register selected by MATCHSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_H_STATE_</name>		
							<description>Selects the H state and the H match register selected by MATCHSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>OUTSEL</name>				
					<description>Input/output select</description>				
					<bitRange>[5:5]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_INPUTS_E</name>		
							<description>Selects the inputs elected by IOSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_OUTPUTS_</name>		
							<description>Selects the outputs selected by IOSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>IOSEL</name>				
					<description>Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event.</description>				
					<bitRange>[9:6]</bitRange>				
					
				</field>					
				<field>					
					<name>IOCOND</name>				
					<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .</description>				
					<bitRange>[11:10]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>LOW</name>		
							<description>LOW</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>RISE</name>		
							<description>Rise</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>FALL</name>		
							<description>Fall</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>HIGH</name>		
							<description>HIGH</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>COMBMODE</name>				
					<description>Selects how the specified match and I/O condition are used and combined.</description>				
					<bitRange>[13:12]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>OR_THE_EVENT_OCCURS</name>		
							<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>MATCH_USES_THE_SPEC</name>		
							<description>MATCH. Uses the specified match only.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>IO_USES_THE_SPECIFI</name>		
							<description>IO. Uses the specified I/O condition only.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>AND_THE_EVENT_OCCUR</name>		
							<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATELD</name>				
					<description>This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.</description>				
					<bitRange>[14:14]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_ADDE</name>		
							<description>STATEV value is added into STATE (the carry-out is ignored).</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_LOAD</name>		
							<description>STATEV value is loaded into STATE.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATEV</name>				
					<description>This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value.</description>				
					<bitRange>[19:15]</bitRange>				
					
				</field>					
				<field>					
					<name>MATCHMEM</name>				
					<description>If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value.</description>				
					<bitRange>[20:20]</bitRange>				
					
				</field>					
				<field>					
					<name>DIRECTION</name>				
					<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>				
					<bitRange>[22:21]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>DIRECTION_INDEPENDEN</name>		
							<description>Direction independent. This event is triggered regardless of the count direction.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_UP_THIS_EV</name>		
							<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_DOWN_THIS_</name>		
							<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>RESERVED</name>				
					<description>Reserved</description>				
					<bitRange>[31:23]</bitRange>				
					
				</field>					
			</fields>						
		</register>	
		<register>
			
			<name>EV2_STATE</name>
			<description>SCT event state register 2</description>
			<addressOffset>0x310</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATEMSKm</name>
					<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1).</description>
					<bitRange>[1:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:2]</bitRange>
				</field>
			</fields>
		</register>
		<register>							
			
			<name>EV2_CTRL</name>						
			<description>SCT event control register 2</description>						
			<addressOffset>0x314</addressOffset>						
			<access>read-write</access>						
			<resetValue>0x00000000</resetValue>						
			<resetMask>0xFFFFFFFF</resetMask>						
			<fields>						
				<field>					
					<name>MATCHSEL</name>				
					<description>Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running.</description>				
					<bitRange>[3:0]</bitRange>				
					
				</field>					
				<field>					
					<name>HEVENT</name>				
					<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>				
					<bitRange>[4:4]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_L_STATE_</name>		
							<description>Selects the L state and the L match register selected by MATCHSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_H_STATE_</name>		
							<description>Selects the H state and the H match register selected by MATCHSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>OUTSEL</name>				
					<description>Input/output select</description>				
					<bitRange>[5:5]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_INPUTS_E</name>		
							<description>Selects the inputs elected by IOSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_OUTPUTS_</name>		
							<description>Selects the outputs selected by IOSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>IOSEL</name>				
					<description>Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event.</description>				
					<bitRange>[9:6]</bitRange>				
					
				</field>					
				<field>					
					<name>IOCOND</name>				
					<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .</description>				
					<bitRange>[11:10]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>LOW</name>		
							<description>LOW</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>RISE</name>		
							<description>Rise</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>FALL</name>		
							<description>Fall</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>HIGH</name>		
							<description>HIGH</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>COMBMODE</name>				
					<description>Selects how the specified match and I/O condition are used and combined.</description>				
					<bitRange>[13:12]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>OR_THE_EVENT_OCCURS</name>		
							<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>MATCH_USES_THE_SPEC</name>		
							<description>MATCH. Uses the specified match only.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>IO_USES_THE_SPECIFI</name>		
							<description>IO. Uses the specified I/O condition only.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>AND_THE_EVENT_OCCUR</name>		
							<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATELD</name>				
					<description>This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.</description>				
					<bitRange>[14:14]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_ADDE</name>		
							<description>STATEV value is added into STATE (the carry-out is ignored).</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_LOAD</name>		
							<description>STATEV value is loaded into STATE.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATEV</name>				
					<description>This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value.</description>				
					<bitRange>[19:15]</bitRange>				
					
				</field>					
				<field>					
					<name>MATCHMEM</name>				
					<description>If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value.</description>				
					<bitRange>[20:20]</bitRange>				
					
				</field>					
				<field>					
					<name>DIRECTION</name>				
					<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>				
					<bitRange>[22:21]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>DIRECTION_INDEPENDEN</name>		
							<description>Direction independent. This event is triggered regardless of the count direction.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_UP_THIS_EV</name>		
							<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_DOWN_THIS_</name>		
							<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>RESERVED</name>				
					<description>Reserved</description>				
					<bitRange>[31:23]</bitRange>				
					
				</field>					
			</fields>						
		</register>	
		<register>
			
			<name>EV3_STATE</name>
			<description>SCT event state register 3</description>
			<addressOffset>0x318</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATEMSKm</name>
					<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1).</description>
					<bitRange>[1:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:2]</bitRange>
				</field>
			</fields>
		</register>
		<register>							
			
			<name>EV3_CTRL</name>						
			<description>SCT event control register 3</description>						
			<addressOffset>0x31C</addressOffset>						
			<access>read-write</access>						
			<resetValue>0x00000000</resetValue>						
			<resetMask>0xFFFFFFFF</resetMask>						
			<fields>						
				<field>					
					<name>MATCHSEL</name>				
					<description>Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running.</description>				
					<bitRange>[3:0]</bitRange>				
					
				</field>					
				<field>					
					<name>HEVENT</name>				
					<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>				
					<bitRange>[4:4]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_L_STATE_</name>		
							<description>Selects the L state and the L match register selected by MATCHSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_H_STATE_</name>		
							<description>Selects the H state and the H match register selected by MATCHSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>OUTSEL</name>				
					<description>Input/output select</description>				
					<bitRange>[5:5]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_INPUTS_E</name>		
							<description>Selects the inputs elected by IOSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_OUTPUTS_</name>		
							<description>Selects the outputs selected by IOSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>IOSEL</name>				
					<description>Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event.</description>				
					<bitRange>[9:6]</bitRange>				
					
				</field>					
				<field>					
					<name>IOCOND</name>				
					<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .</description>				
					<bitRange>[11:10]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>LOW</name>		
							<description>LOW</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>RISE</name>		
							<description>Rise</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>FALL</name>		
							<description>Fall</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>HIGH</name>		
							<description>HIGH</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>COMBMODE</name>				
					<description>Selects how the specified match and I/O condition are used and combined.</description>				
					<bitRange>[13:12]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>OR_THE_EVENT_OCCURS</name>		
							<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>MATCH_USES_THE_SPEC</name>		
							<description>MATCH. Uses the specified match only.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>IO_USES_THE_SPECIFI</name>		
							<description>IO. Uses the specified I/O condition only.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>AND_THE_EVENT_OCCUR</name>		
							<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATELD</name>				
					<description>This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.</description>				
					<bitRange>[14:14]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_ADDE</name>		
							<description>STATEV value is added into STATE (the carry-out is ignored).</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_LOAD</name>		
							<description>STATEV value is loaded into STATE.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATEV</name>				
					<description>This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value.</description>				
					<bitRange>[19:15]</bitRange>				
					
				</field>					
				<field>					
					<name>MATCHMEM</name>				
					<description>If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value.</description>				
					<bitRange>[20:20]</bitRange>				
					
				</field>					
				<field>					
					<name>DIRECTION</name>				
					<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>				
					<bitRange>[22:21]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>DIRECTION_INDEPENDEN</name>		
							<description>Direction independent. This event is triggered regardless of the count direction.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_UP_THIS_EV</name>		
							<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_DOWN_THIS_</name>		
							<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>RESERVED</name>				
					<description>Reserved</description>				
					<bitRange>[31:23]</bitRange>				
					
				</field>					
			</fields>						
		</register>	
		<register>
			
			<name>EV4_STATE</name>
			<description>SCT event state register 4</description>
			<addressOffset>0x320</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATEMSKm</name>
					<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1).</description>
					<bitRange>[1:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:2]</bitRange>
				</field>
			</fields>
		</register>
		<register>							
			
			<name>EV4_CTRL</name>						
			<description>SCT event control register 4</description>						
			<addressOffset>0x324</addressOffset>						
			<access>read-write</access>						
			<resetValue>0x00000000</resetValue>						
			<resetMask>0xFFFFFFFF</resetMask>						
			<fields>						
				<field>					
					<name>MATCHSEL</name>				
					<description>Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running.</description>				
					<bitRange>[3:0]</bitRange>				
					
				</field>					
				<field>					
					<name>HEVENT</name>				
					<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>				
					<bitRange>[4:4]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_L_STATE_</name>		
							<description>Selects the L state and the L match register selected by MATCHSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_H_STATE_</name>		
							<description>Selects the H state and the H match register selected by MATCHSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>OUTSEL</name>				
					<description>Input/output select</description>				
					<bitRange>[5:5]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_INPUTS_E</name>		
							<description>Selects the inputs elected by IOSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_OUTPUTS_</name>		
							<description>Selects the outputs selected by IOSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>IOSEL</name>				
					<description>Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event.</description>				
					<bitRange>[9:6]</bitRange>				
					
				</field>					
				<field>					
					<name>IOCOND</name>				
					<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .</description>				
					<bitRange>[11:10]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>LOW</name>		
							<description>LOW</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>RISE</name>		
							<description>Rise</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>FALL</name>		
							<description>Fall</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>HIGH</name>		
							<description>HIGH</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>COMBMODE</name>				
					<description>Selects how the specified match and I/O condition are used and combined.</description>				
					<bitRange>[13:12]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>OR_THE_EVENT_OCCURS</name>		
							<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>MATCH_USES_THE_SPEC</name>		
							<description>MATCH. Uses the specified match only.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>IO_USES_THE_SPECIFI</name>		
							<description>IO. Uses the specified I/O condition only.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>AND_THE_EVENT_OCCUR</name>		
							<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATELD</name>				
					<description>This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.</description>				
					<bitRange>[14:14]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_ADDE</name>		
							<description>STATEV value is added into STATE (the carry-out is ignored).</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_LOAD</name>		
							<description>STATEV value is loaded into STATE.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATEV</name>				
					<description>This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value.</description>				
					<bitRange>[19:15]</bitRange>				
					
				</field>					
				<field>					
					<name>MATCHMEM</name>				
					<description>If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value.</description>				
					<bitRange>[20:20]</bitRange>				
					
				</field>					
				<field>					
					<name>DIRECTION</name>				
					<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>				
					<bitRange>[22:21]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>DIRECTION_INDEPENDEN</name>		
							<description>Direction independent. This event is triggered regardless of the count direction.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_UP_THIS_EV</name>		
							<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_DOWN_THIS_</name>		
							<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>RESERVED</name>				
					<description>Reserved</description>				
					<bitRange>[31:23]</bitRange>				
					
				</field>					
			</fields>						
		</register>	
		<register>
			
			<name>EV5_STATE</name>
			<description>SCT event state register 5</description>
			<addressOffset>0x328</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>STATEMSKm</name>
					<description>If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1).</description>
					<bitRange>[1:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:2]</bitRange>
				</field>
			</fields>
		</register>
		<register>							
			
			<name>EV5_CTRL</name>						
			<description>SCT event control register 5</description>						
			<addressOffset>0x32C</addressOffset>						
			<access>read-write</access>						
			<resetValue>0x00000000</resetValue>						
			<resetMask>0xFFFFFFFF</resetMask>						
			<fields>						
				<field>					
					<name>MATCHSEL</name>				
					<description>Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running.</description>				
					<bitRange>[3:0]</bitRange>				
					
				</field>					
				<field>					
					<name>HEVENT</name>				
					<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>				
					<bitRange>[4:4]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_L_STATE_</name>		
							<description>Selects the L state and the L match register selected by MATCHSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_H_STATE_</name>		
							<description>Selects the H state and the H match register selected by MATCHSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>OUTSEL</name>				
					<description>Input/output select</description>				
					<bitRange>[5:5]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>SELECTS_THE_INPUTS_E</name>		
							<description>Selects the inputs elected by IOSEL.</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>SELECTS_THE_OUTPUTS_</name>		
							<description>Selects the outputs selected by IOSEL.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>IOSEL</name>				
					<description>Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event.</description>				
					<bitRange>[9:6]</bitRange>				
					
				</field>					
				<field>					
					<name>IOCOND</name>				
					<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .</description>				
					<bitRange>[11:10]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>LOW</name>		
							<description>LOW</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>RISE</name>		
							<description>Rise</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>FALL</name>		
							<description>Fall</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>HIGH</name>		
							<description>HIGH</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>COMBMODE</name>				
					<description>Selects how the specified match and I/O condition are used and combined.</description>				
					<bitRange>[13:12]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>OR_THE_EVENT_OCCURS</name>		
							<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>MATCH_USES_THE_SPEC</name>		
							<description>MATCH. Uses the specified match only.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>IO_USES_THE_SPECIFI</name>		
							<description>IO. Uses the specified I/O condition only.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>AND_THE_EVENT_OCCUR</name>		
							<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>		
							<value>0x3</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATELD</name>				
					<description>This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.</description>				
					<bitRange>[14:14]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_ADDE</name>		
							<description>STATEV value is added into STATE (the carry-out is ignored).</description>		
							<value>0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>STATEV_VALUE_IS_LOAD</name>		
							<description>STATEV value is loaded into STATE.</description>		
							<value>1</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>STATEV</name>				
					<description>This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value.</description>				
					<bitRange>[19:15]</bitRange>				
					
				</field>					
				<field>					
					<name>MATCHMEM</name>				
					<description>If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value.</description>				
					<bitRange>[20:20]</bitRange>				
					
				</field>					
				<field>					
					<name>DIRECTION</name>				
					<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>				
					<bitRange>[22:21]</bitRange>				
					<enumeratedValues>				
						<name>ENUM</name>				
						<enumeratedValue>			
							<name>DIRECTION_INDEPENDEN</name>		
							<description>Direction independent. This event is triggered regardless of the count direction.</description>		
							<value>0x0</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_UP_THIS_EV</name>		
							<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>		
							<value>0x1</value>		
						</enumeratedValue>			
						<enumeratedValue>			
							<name>COUNTING_DOWN_THIS_</name>		
							<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>		
							<value>0x2</value>		
						</enumeratedValue>			
					</enumeratedValues>				
				</field>					
				<field>					
					<name>RESERVED</name>				
					<description>Reserved</description>				
					<bitRange>[31:23]</bitRange>				
					
				</field>					
			</fields>						
		</register>	
		<register>
			
			<name>OUT0_SET</name>
			<description>SCT output 0 set register</description>
			<addressOffset>0x500</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SET</name>
					<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT0_CLR</name>
			<description>SCT output 0 clear register</description>
			<addressOffset>0x504</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CLR</name>
					<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT1_SET</name>
			<description>SCT output 1 set register</description>
			<addressOffset>0x508</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SET</name>
					<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT1_CLR</name>
			<description>SCT output 1 clear register</description>
			<addressOffset>0x50C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CLR</name>
					<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT2_SET</name>
			<description>SCT output 2 set register</description>
			<addressOffset>0x510</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SET</name>
					<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT2_CLR</name>
			<description>SCT output 2 clear register</description>
			<addressOffset>0x514</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CLR</name>
					<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT3_SET</name>
			<description>SCT output 3 set register</description>
			<addressOffset>0x518</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SET</name>
					<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			
			<name>OUT3_CLR</name>
			<description>SCT output 3 clear register</description>
			<addressOffset>0x51C</addressOffset>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>CLR</name>
					<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5.</description>
					<bitRange>[5:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved</description>
					<bitRange>[31:6]</bitRange>
				</field>
			</fields>
		</register>
	</registers>
</peripheral>


		<peripheral>
			<name>GPIO_PORT</name>
			<description>General Purpose I/O port (GPIO)</description>
			<groupName>GPIO_PORT</groupName>
			<baseAddress>0xA0000000</baseAddress>
			<addressBlock>
				<offset>0x0</offset>
				<size>0xFFFFF</size>
				<usage>registers</usage>
			</addressBlock>
			<registers>
				<register>
					<dim>18</dim>
					<dimIncrement>0x1</dimIncrement>
					<dimIndex>0-17</dimIndex>
					<name>B%s</name>
				
					<description>Byte pin registers port 0; pins PIO0_0 to PIO0_17</description>
					<addressOffset>0x0000</addressOffset>
					<size>8</size>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>PBYTE</name>
							<description>Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
							<bitRange>[0:0]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<dim>18</dim>
					<dimIncrement>0x4</dimIncrement>
					<dimIndex>0-17</dimIndex>
					<name>W%s</name>
					<description>Word pin registers port 0</description>
					<addressOffset>0x1000</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>PWORD</name>
							<description>Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit.</description>
							<bitRange>[31:0]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>DIR0</name>
					<description>Direction registers port 0</description>
					<addressOffset>0x2000</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>DIRP0</name>
							<description>Selects pin direction for pin P0_n (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = input. 1 = output.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>MASK0</name>
					<description>Mask register port 0</description>
					<addressOffset>0x2080</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>MASKP0</name>
							<description>Controls which bits corresponding to P0_n are active in the P0MPORT register (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>PIN0</name>
					<description>Port pin register port 0</description>
					<addressOffset>0x2100</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>PORT0</name>
							<description>Reads pin states or loads output bits (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>MPIN0</name>
					<description>Masked port register port 0</description>
					<addressOffset>0x2180</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>MPORTP0</name>
							<description>Masked port register (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>SET0</name>
					<description>Write: Set register for port 0 Read: output bits for port 0</description>
					<addressOffset>0x2200</addressOffset>
					<access>read-write</access>
					<resetValue>0</resetValue>
					<resetMask>0xFFFFFFFF</resetMask>
					<fields>
						<field>
							<name>SETP0</name>
							<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>CLR0</name>
					<description>Clear port 0</description>
					<addressOffset>0x2280</addressOffset>
					<access>write-only</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>CLRP0</name>
							<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
				<register>
					<name>NOT0</name>
					<description>Toggle port 0</description>
					<addressOffset>0x2300</addressOffset>
					<access>write-only</access>
					<resetValue>0</resetValue>
					<resetMask>0x00000000</resetMask>
					<fields>
						<field>
							<name>NOTP0</name>
							<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
							<bitRange>[17:0]</bitRange>
						</field>
						<field>
							<name>RESERVED</name>
							<description>Reserved.</description>
							<bitRange>[31:18]</bitRange>
						</field>
					</fields>
				</register>
			</registers>
		</peripheral>
		
		
		<peripheral>
	<name>PIN_INT</name>
	<description>Pin interrupt and  pattern match engine</description>
	<groupName>GPIO_PIN_INT</groupName>
	<baseAddress>0xA0004000</baseAddress>
	<addressBlock>
	<offset>0x0</offset>
	<size>0xFFF</size>
	<usage>registers</usage>
	</addressBlock>
	<interrupt>
	<name>PININT0</name>
	<value>24</value>
	</interrupt>
	<interrupt>
	<name>PININT1</name>
	<value>25</value>
	</interrupt>
	<interrupt>
	<name>PININT2</name>
	<value>26</value>
	</interrupt>
	<interrupt>
	<name>PININT3</name>
	<value>27</value>
	</interrupt>
	<interrupt>
	<name>PININT4</name>
	<value>28</value>
	</interrupt>
	<interrupt>
	<name>PININT5</name>
	<value>29</value>
	</interrupt>
	<interrupt>
	<name>PININT6</name>
	<value>30</value>
	</interrupt>
	<interrupt>
	<name>PININT7</name>
	<value>31</value>
	</interrupt>
	<registers>
		<register>
			<name>ISEL</name>
			<description>Pin Interrupt Mode register</description>
			<addressOffset>0x000</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>PMODE</name>
					<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>IENR</name>
			<description>Pin interrupt level or rising edge interrupt enable register</description>
			<addressOffset>0x004</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>ENRL</name>
					<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>SIENR</name>
			<description>Pin interrupt level (rising edge) interrupt set register</description>
			<addressOffset>0x008</addressOffset>
			<access>write-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<fields>
				<field>
					<name>SETENRL</name>
					<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>CIENR</name>
			<description>Pin interrupt level  or rising edge interrupt clear register</description>
			<addressOffset>0x00C</addressOffset>
			<access>write-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<fields>
				<field>
					<name>CENRL</name>
					<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>IENF</name>
			<description>Pin interrupt active level or falling edge interrupt enable register</description>
			<addressOffset>0x010</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>ENAF</name>
					<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>SIENF</name>
			<description>Pin interrupt active level or falling edge interrupt set register</description>
			<addressOffset>0x014</addressOffset>
			<access>write-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<fields>
				<field>
					<name>SETENAF</name>
					<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>CIENF</name>
			<description>Pin interrupt active level (falling edge) interrupt clear register</description>
			<addressOffset>0x018</addressOffset>
			<access>write-only</access>
			<resetValue>0</resetValue>
			<resetMask>0x00000000</resetMask>
			<fields>
				<field>
					<name>CENAF</name>
					<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>RISE</name>
			<description>Pin interrupt rising edge register</description>
			<addressOffset>0x01C</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>RDET</name>
					<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>FALL</name>
			<description>Pin interrupt falling edge register</description>
			<addressOffset>0x020</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>FDET</name>
					<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>IST</name>
			<description>Pin interrupt status register</description>
			<addressOffset>0x024</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>PSTAT</name>
					<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
					<bitRange>[7:0]</bitRange>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved.</description>
					<bitRange>[31:8]</bitRange>
				</field>
			</fields>
		</register>
		<register>
			<name>PMCTRL</name>
			<description>GPIO pattern match interrupt control register</description>
			<addressOffset>0x028</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>SEL_PMATCH</name>
					<description>Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.</description>
					<bitRange>[0:0]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>PIN_INTERRUPT_INTER</name>
							<description>Pin interrupt. Interrupts are driven in response to the standard pin interrupt function</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>PATTERN_MATCH_INTER</name>
							<description>Pattern match. Interrupts are driven in response to pattern matches.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>ENA_RXEV</name>
					<description>Enables the RxEv output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.</description>
					<bitRange>[1:1]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>DISABLED_RXEV_OUTPU</name>
							<description>Disabled. RxEv output to the cpu is disabled.</description>
							<value>0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>ENABLED_RXEV_OUTPUT</name>
							<description>Enabled. RxEv output to the cpu is enabled.</description>
							<value>1</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>RESERVED</name>
					<description>Reserved. Do not write 1s to unused bits.</description>
					<bitRange>[23:2]</bitRange>
					
				</field>
				<field>
					<name>PMAT</name>
					<description>This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.</description>
					<bitRange>[31:24]</bitRange>
					
				</field>
			</fields>
		</register>
		<register>
			<name>PMSRC</name>
			<description>GPIO pattern match interrupt bit-slice source register</description>
			<addressOffset>0x02C</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>Reserved</name>
					<description>Software should not write 1s to unused bits.</description>
					<bitRange>[7:0]</bitRange>
					
				</field>
				<field>
					<name>SRC0</name>
					<description>Selects the input source for bit slice 0</description>
					<bitRange>[10:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 0.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 0.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 0.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 0.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 0.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 0.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 0.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 0.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC1</name>
					<description>Selects the input source for bit slice 1</description>
					<bitRange>[13:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 1.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 1.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 1.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 1.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 1.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 1.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 1.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 1.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC2</name>
					<description>Selects the input source for bit slice 2</description>
					<bitRange>[16:14]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 2.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 2.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 2.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 2.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 2.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 2.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 2.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 2.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC3</name>
					<description>Selects the input source for bit slice 3</description>
					<bitRange>[19:17]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 3.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 3.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 3.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 3.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 3.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 3.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 3.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 3.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC4</name>
					<description>Selects the input source for bit slice 4</description>
					<bitRange>[22:20]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 4.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 4.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 4.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 4.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 4.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 4.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 4.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 4.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC5</name>
					<description>Selects the input source for bit slice 5</description>
					<bitRange>[25:23]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 5.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 5.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 5.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 5.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 5.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 5.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 5.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 5.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC6</name>
					<description>Selects the input source for bit slice 6</description>
					<bitRange>[28:26]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 6.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 6.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 6.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 6.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 6.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 6.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 6.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 6.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>SRC7</name>
					<description>Selects the input source for bit slice 7</description>
					<bitRange>[31:29]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>INPUT_0_SELECTS_PIN</name>
							<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 7.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_1_SELECTS_PIN</name>
							<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 7.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_2_SELECTS_PIN</name>
							<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 7.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_3_SELECTS_PIN</name>
							<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 7.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_4_SELECTS_PIN</name>
							<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 7.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_5_SELECTS_PIN</name>
							<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 7.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_6_SELECTS_PIN</name>
							<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 7.</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>INPUT_7_SELECTS_PIN</name>
							<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 7.</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
			</fields>
		</register>
		<register>
			<name>PMCFG</name>
			<description>GPIO pattern match interrupt bit slice configuration register</description>
			<addressOffset>0x030</addressOffset>
			<access>read-write</access>
			<resetValue>0</resetValue>
			<resetMask>0xFFFFFFFF</resetMask>
			<fields>
				<field>
					<name>PROD_ENDPTS</name>
					<description>A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression.  This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice).</description>
					<bitRange>[6:0]</bitRange>
					
				</field>
				<field>
					<name>Reserved</name>
					<description>(Bit slice 7 is automatically considered a product end point)  Software should not write 1s to unused bits</description>
					<bitRange>[7:7]</bitRange>
					
				</field>
				<field>
					<name>CFG0</name>
					<description>Specifies the match-contribution condition for bit slice 0.</description>
					<bitRange>[10:8]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG1</name>
					<description>Specifies the match-contribution condition for bit slice 1.</description>
					<bitRange>[13:11]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG2</name>
					<description>Specifies the match-contribution condition for bit slice 2.</description>
					<bitRange>[16:14]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG3</name>
					<description>Specifies the match-contribution condition for bit slice 3.</description>
					<bitRange>[19:17]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG4</name>
					<description>Specifies the match-contribution condition for bit slice 4.</description>
					<bitRange>[22:20]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG5</name>
					<description>Specifies the match-contribution condition for bit slice 5.</description>
					<bitRange>[25:23]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG6</name>
					<description>Specifies the match-contribution condition for bit slice 6.</description>
					<bitRange>[28:26]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
				<field>
					<name>CFG7</name>
					<description>Specifies the match-contribution condition for bit slice 7.</description>
					<bitRange>[31:29]</bitRange>
					<enumeratedValues>
					<name>ENUM</name>
						<enumeratedValue>
							<name>CONSTANT_1_THIS_BIT</name>
							<description>Constant 1. This bit slice always contributes to a product term match.</description>
							<value>0x0</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_EDGE_MATCH_O</name>
							<description>Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x1</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>FALLING_EDGE_MATCH_</name>
							<description>Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x2</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>RISING_OR_FALLING_ED</name>
							<description>Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.</description>
							<value>0x3</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>HIGH_LEVEL_MATCH_F</name>
							<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
							<value>0x4</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>LOW_LEVEL_MATCH_OCC</name>
							<description>Low level. Match occurs when there is a low level on the specified input.</description>
							<value>0x5</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>CONSTANT_0_THIS_BIT</name>
							<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)</description>
							<value>0x6</value>
						</enumeratedValue>
						<enumeratedValue>
							<name>EVENT_MATCH_OCCURS_</name>
							<description>Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)</description>
							<value>0x7</value>
						</enumeratedValue>
					</enumeratedValues>
				</field>
			</fields>
		</register>
	</registers>
</peripheral>



	</peripherals>
</device>