Module lpc55s6x_pac::spi0::fifowr

FIFO write data.

Structs

EOF_W	Write proxy for field EOF
EOT_W	Write proxy for field EOT
LEN_W	Write proxy for field LEN
RXIGNORE_W	Write proxy for field RXIGNORE
TXDATA_W	Write proxy for field TXDATA
TXSSEL0_N_W	Write proxy for field TXSSEL0_N
TXSSEL1_N_W	Write proxy for field TXSSEL1_N
TXSSEL2_N_W	Write proxy for field TXSSEL2_N
TXSSEL3_N_W	Write proxy for field TXSSEL3_N

Enums

EOF_AW	End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
EOT_AW	End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register.
RXIGNORE_AW	Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.
TXSSEL0_N_AW	Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
TXSSEL1_N_AW	Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
TXSSEL2_N_AW	Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
TXSSEL3_N_AW	Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.

Type Definitions

R	Reader of register FIFOWR
W	Writer for register FIFOWR