[−][src]Module lpc55s6x_pac::ctimer0::ctcr
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Structs
CINSEL_W | Write proxy for field |
CTMODE_W | Write proxy for field |
ENCC_W | Write proxy for field |
SELCC_W | Write proxy for field |
Enums
CINSEL_A | Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. |
CTMODE_A | Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. |
SELCC_A | Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. |
Type Definitions
CINSEL_R | Reader of field |
CTMODE_R | Reader of field |
ENCC_R | Reader of field |
R | Reader of register CTCR |
SELCC_R | Reader of field |
W | Writer for register CTCR |