[−][src]Type Definition lpc55s6x_pac::syscon::sdioclkctrl::W
type W = W<u32, SDIOCLKCTRL>;
Writer for register SDIOCLKCTRL
Methods
impl W[src]
pub fn cclk_drv_phase(&mut self) -> CCLK_DRV_PHASE_W[src]
Bits 0:1 - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
pub fn cclk_sample_phase(&mut self) -> CCLK_SAMPLE_PHASE_W[src]
Bits 2:3 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
pub fn phase_active(&mut self) -> PHASE_ACTIVE_W[src]
Bit 7 - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
pub fn cclk_drv_delay(&mut self) -> CCLK_DRV_DELAY_W[src]
Bits 16:20 - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
pub fn cclk_drv_delay_active(&mut self) -> CCLK_DRV_DELAY_ACTIVE_W[src]
Bit 23 - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
pub fn cclk_sample_delay(&mut self) -> CCLK_SAMPLE_DELAY_W[src]
Bits 24:28 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
pub fn cclk_sample_delay_active(&mut self) -> CCLK_SAMPLE_DELAY_ACTIVE_W[src]
Bit 31 - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.