[][src]Type Definition lpc55s6x_pac::usbphy::ctrl_tog::W

type W = W<u32, CTRL_TOG>;

Writer for register CTRL_TOG

Methods

impl W[src]

pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W[src]

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W[src]

Bit 3 - Indicates that the device has disconnected in High-Speed mode

pub fn endevplugindet(&mut self) -> ENDEVPLUGINDET_W[src]

Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode

pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W[src]

Bit 12 - Indicates that the device is connected

pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W[src]

Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY

pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W[src]

Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY

pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W[src]

Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)

pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W[src]

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W[src]

Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended

pub fn fsdll_rst_en(&mut self) -> FSDLL_RST_EN_W[src]

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn otg_id_value(&mut self) -> OTG_ID_VALUE_W[src]

Bit 27 - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle

pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W[src]

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing

pub fn utmi_suspendm(&mut self) -> UTMI_SUSPENDM_W[src]

Bit 29 - Used by the PHY to indicate a powered-down state

pub fn clkgate(&mut self) -> CLKGATE_W[src]

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&mut self) -> SFTRST_W[src]

Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers