Type Definition lpc55s6x_pac::spi0::fifowr::W

type W = W<u32, FIFOWR>;

Writer for register FIFOWR

Methods

impl W

pub fn txdata(&mut self) -> TXDATA_W

Bits 0:15 - Transmit data to the FIFO.

pub fn txssel0_n(&mut self) -> TXSSEL0_N_W

Bit 16 - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.

pub fn txssel1_n(&mut self) -> TXSSEL1_N_W

Bit 17 - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.

pub fn txssel2_n(&mut self) -> TXSSEL2_N_W

Bit 18 - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.

pub fn txssel3_n(&mut self) -> TXSSEL3_N_W

Bit 19 - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.

pub fn eot(&mut self) -> EOT_W

Bit 20 - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register.

pub fn eof(&mut self) -> EOF_W

Bit 21 - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.

pub fn rxignore(&mut self) -> RXIGNORE_W

Bit 22 - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.

pub fn len(&mut self) -> LEN_W

Bits 24:27 - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length.