[−][src]Module lpc55s6x_pac::prince
PRINCE
Modules
| base_addr0 | Base Address for region 0 register |
| base_addr1 | Base Address for region 1 register |
| base_addr2 | Base Address for region 2 register |
| enc_enable | Encryption Enable register |
| iv_lsb0 | Initial Vector register for region 0, Least Significant Bits |
| iv_lsb1 | Initial Vector register for region 1, Least Significant Bits |
| iv_lsb2 | Initial Vector register for region 2, Least Significant Bits |
| iv_msb0 | Initial Vector register for region 0, Most Significant Bits |
| iv_msb1 | Initial Vector register for region 1, Most Significant Bits |
| iv_msb2 | Initial Vector register for region 2, Most Significant Bits |
| lock | Lock register |
| mask_lsb | Data Mask register, 32 Least Significant Bits |
| mask_msb | Data Mask register, 32 Most Significant Bits |
| sr_enable0 | Sub-Region Enable register for region 0 |
| sr_enable1 | Sub-Region Enable register for region 1 |
| sr_enable2 | Sub-Region Enable register for region 2 |
Structs
| RegisterBlock | Register block |
Type Definitions
| BASE_ADDR0 | Base Address for region 0 register |
| BASE_ADDR1 | Base Address for region 1 register |
| BASE_ADDR2 | Base Address for region 2 register |
| ENC_ENABLE | Encryption Enable register |
| IV_LSB0 | Initial Vector register for region 0, Least Significant Bits |
| IV_LSB1 | Initial Vector register for region 1, Least Significant Bits |
| IV_LSB2 | Initial Vector register for region 2, Least Significant Bits |
| IV_MSB0 | Initial Vector register for region 0, Most Significant Bits |
| IV_MSB1 | Initial Vector register for region 1, Most Significant Bits |
| IV_MSB2 | Initial Vector register for region 2, Most Significant Bits |
| LOCK | Lock register |
| MASK_LSB | Data Mask register, 32 Least Significant Bits |
| MASK_MSB | Data Mask register, 32 Most Significant Bits |
| SR_ENABLE0 | Sub-Region Enable register for region 0 |
| SR_ENABLE1 | Sub-Region Enable register for region 1 |
| SR_ENABLE2 | Sub-Region Enable register for region 2 |