[−][src]Struct lpc55s6x_pac::ahb_secure_ctrl::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub sec_ctrl_flash_rom_slave_rule: SEC_CTRL_FLASH_ROM_SLAVE_RULE,
    pub sec_ctrl_flash_mem_rule0: SEC_CTRL_FLASH_MEM_RULE0,
    pub sec_ctrl_flash_mem_rule1: SEC_CTRL_FLASH_MEM_RULE1,
    pub sec_ctrl_flash_mem_rule2: SEC_CTRL_FLASH_MEM_RULE2,
    pub sec_ctrl_rom_mem_rule0: SEC_CTRL_ROM_MEM_RULE0,
    pub sec_ctrl_rom_mem_rule1: SEC_CTRL_ROM_MEM_RULE1,
    pub sec_ctrl_rom_mem_rule2: SEC_CTRL_ROM_MEM_RULE2,
    pub sec_ctrl_rom_mem_rule3: SEC_CTRL_ROM_MEM_RULE3,
    pub sec_ctrl_ramx_slave_rule: SEC_CTRL_RAMX_SLAVE_RULE,
    pub sec_ctrl_ramx_mem_rule0: SEC_CTRL_RAMX_MEM_RULE0,
    pub sec_ctrl_ram0_slave_rule: SEC_CTRL_RAM0_SLAVE_RULE,
    pub sec_ctrl_ram0_mem_rule0: SEC_CTRL_RAM0_MEM_RULE0,
    pub sec_ctrl_ram0_mem_rule1: SEC_CTRL_RAM0_MEM_RULE1,
    pub sec_ctrl_ram1_slave_rule: SEC_CTRL_RAM1_SLAVE_RULE,
    pub sec_ctrl_ram1_mem_rule0: SEC_CTRL_RAM1_MEM_RULE0,
    pub sec_ctrl_ram1_mem_rule1: SEC_CTRL_RAM1_MEM_RULE1,
    pub sec_ctrl_ram2_slave_rule: SEC_CTRL_RAM2_SLAVE_RULE,
    pub sec_ctrl_ram2_mem_rule0: SEC_CTRL_RAM2_MEM_RULE0,
    pub sec_ctrl_ram2_mem_rule1: SEC_CTRL_RAM2_MEM_RULE1,
    pub sec_ctrl_ram3_slave_rule: SEC_CTRL_RAM3_SLAVE_RULE,
    pub sec_ctrl_ram3_mem_rule0: SEC_CTRL_RAM3_MEM_RULE0,
    pub sec_ctrl_ram3_mem_rule1: SEC_CTRL_RAM3_MEM_RULE1,
    pub sec_ctrl_ram4_slave_rule: SEC_CTRL_RAM4_SLAVE_RULE,
    pub sec_ctrl_ram4_mem_rule0: SEC_CTRL_RAM4_MEM_RULE0,
    pub sec_ctrl_apb_bridge_slave_rule: SEC_CTRL_APB_BRIDGE_SLAVE_RULE,
    pub sec_ctrl_apb_bridge0_mem_ctrl0: SEC_CTRL_APB_BRIDGE0_MEM_CTRL0,
    pub sec_ctrl_apb_bridge0_mem_ctrl1: SEC_CTRL_APB_BRIDGE0_MEM_CTRL1,
    pub sec_ctrl_apb_bridge0_mem_ctrl2: SEC_CTRL_APB_BRIDGE0_MEM_CTRL2,
    pub sec_ctrl_apb_bridge0_mem_ctrl3: SEC_CTRL_APB_BRIDGE0_MEM_CTRL3,
    pub sec_ctrl_apb_bridge1_mem_ctrl0: SEC_CTRL_APB_BRIDGE1_MEM_CTRL0,
    pub sec_ctrl_apb_bridge1_mem_ctrl1: SEC_CTRL_APB_BRIDGE1_MEM_CTRL1,
    pub sec_ctrl_apb_bridge1_mem_ctrl2: SEC_CTRL_APB_BRIDGE1_MEM_CTRL2,
    pub sec_ctrl_apb_bridge1_mem_ctrl3: SEC_CTRL_APB_BRIDGE1_MEM_CTRL3,
    pub sec_ctrl_ahb0_0_slave_rule: SEC_CTRL_AHB0_0_SLAVE_RULE,
    pub sec_ctrl_ahb0_1_slave_rule: SEC_CTRL_AHB0_1_SLAVE_RULE,
    pub sec_ctrl_ahb1_0_slave_rule: SEC_CTRL_AHB1_0_SLAVE_RULE,
    pub sec_ctrl_ahb1_1_slave_rule: SEC_CTRL_AHB1_1_SLAVE_RULE,
    pub sec_ctrl_ahb2_0_slave_rule: SEC_CTRL_AHB2_0_SLAVE_RULE,
    pub sec_ctrl_ahb2_1_slave_rule: SEC_CTRL_AHB2_1_SLAVE_RULE,
    pub sec_ctrl_ahb2_0_mem_rule: SEC_CTRL_AHB2_0_MEM_RULE,
    pub sec_ctrl_usb_hs_slave_rule: SEC_CTRL_USB_HS_SLAVE_RULE,
    pub sec_ctrl_usb_hs_mem_rule: SEC_CTRL_USB_HS_MEM_RULE,
    pub sec_vio_addr: [SEC_VIO_ADDR; 12],
    pub sec_vio_misc_info: [SEC_VIO_MISC_INFO; 12],
    pub sec_vio_info_valid: SEC_VIO_INFO_VALID,
    pub sec_gpio_mask0: SEC_GPIO_MASK0,
    pub sec_gpio_mask1: SEC_GPIO_MASK1,
    pub sec_cpu_int_mask0: SEC_CPU_INT_MASK0,
    pub sec_cpu_int_mask1: SEC_CPU_INT_MASK1,
    pub sec_mask_lock: SEC_MASK_LOCK,
    pub master_sec_level: MASTER_SEC_LEVEL,
    pub master_sec_anti_pol_reg: MASTER_SEC_ANTI_POL_REG,
    pub cm33_lock_reg: CM33_LOCK_REG,
    pub mcm33_lock_reg: MCM33_LOCK_REG,
    pub misc_ctrl_dp_reg: MISC_CTRL_DP_REG,
    pub misc_ctrl_reg: MISC_CTRL_REG,
    // some fields omitted
}

Register block

Fields

sec_ctrl_flash_rom_slave_rule: SEC_CTRL_FLASH_ROM_SLAVE_RULE

0x00 - Security access rules for Flash and ROM slaves.

sec_ctrl_flash_mem_rule0: SEC_CTRL_FLASH_MEM_RULE0

0x10 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.

sec_ctrl_flash_mem_rule1: SEC_CTRL_FLASH_MEM_RULE1

0x14 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.

sec_ctrl_flash_mem_rule2: SEC_CTRL_FLASH_MEM_RULE2

0x18 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.

sec_ctrl_rom_mem_rule0: SEC_CTRL_ROM_MEM_RULE0

0x20 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.

sec_ctrl_rom_mem_rule1: SEC_CTRL_ROM_MEM_RULE1

0x24 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.

sec_ctrl_rom_mem_rule2: SEC_CTRL_ROM_MEM_RULE2

0x28 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.

sec_ctrl_rom_mem_rule3: SEC_CTRL_ROM_MEM_RULE3

0x2c - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.

sec_ctrl_ramx_slave_rule: SEC_CTRL_RAMX_SLAVE_RULE

0x30 - Security access rules for RAMX slaves.

sec_ctrl_ramx_mem_rule0: SEC_CTRL_RAMX_MEM_RULE0

0x40 - Security access rules for RAMX slaves.

sec_ctrl_ram0_slave_rule: SEC_CTRL_RAM0_SLAVE_RULE

0x50 - Security access rules for RAM0 slaves.

sec_ctrl_ram0_mem_rule0: SEC_CTRL_RAM0_MEM_RULE0

0x60 - Security access rules for RAM0 slaves.

sec_ctrl_ram0_mem_rule1: SEC_CTRL_RAM0_MEM_RULE1

0x64 - Security access rules for RAM0 slaves.

sec_ctrl_ram1_slave_rule: SEC_CTRL_RAM1_SLAVE_RULE

0x70 - Security access rules for RAM1 slaves.

sec_ctrl_ram1_mem_rule0: SEC_CTRL_RAM1_MEM_RULE0

0x80 - Security access rules for RAM1 slaves.

sec_ctrl_ram1_mem_rule1: SEC_CTRL_RAM1_MEM_RULE1

0x84 - Security access rules for RAM1 slaves.

sec_ctrl_ram2_slave_rule: SEC_CTRL_RAM2_SLAVE_RULE

0x90 - Security access rules for RAM2 slaves.

sec_ctrl_ram2_mem_rule0: SEC_CTRL_RAM2_MEM_RULE0

0xa0 - Security access rules for RAM2 slaves.

sec_ctrl_ram2_mem_rule1: SEC_CTRL_RAM2_MEM_RULE1

0xa4 - Security access rules for RAM2 slaves.

sec_ctrl_ram3_slave_rule: SEC_CTRL_RAM3_SLAVE_RULE

0xb0 - Security access rules for RAM3 slaves.

sec_ctrl_ram3_mem_rule0: SEC_CTRL_RAM3_MEM_RULE0

0xc0 - Security access rules for RAM3 slaves.

sec_ctrl_ram3_mem_rule1: SEC_CTRL_RAM3_MEM_RULE1

0xc4 - Security access rules for RAM3 slaves.

sec_ctrl_ram4_slave_rule: SEC_CTRL_RAM4_SLAVE_RULE

0xd0 - Security access rules for RAM4 slaves.

sec_ctrl_ram4_mem_rule0: SEC_CTRL_RAM4_MEM_RULE0

0xe0 - Security access rules for RAM4 slaves.

sec_ctrl_apb_bridge_slave_rule: SEC_CTRL_APB_BRIDGE_SLAVE_RULE

0xf0 - Security access rules for both APB Bridges slaves.

sec_ctrl_apb_bridge0_mem_ctrl0: SEC_CTRL_APB_BRIDGE0_MEM_CTRL0

0x100 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.

sec_ctrl_apb_bridge0_mem_ctrl1: SEC_CTRL_APB_BRIDGE0_MEM_CTRL1

0x104 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.

sec_ctrl_apb_bridge0_mem_ctrl2: SEC_CTRL_APB_BRIDGE0_MEM_CTRL2

0x108 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.

sec_ctrl_apb_bridge0_mem_ctrl3: SEC_CTRL_APB_BRIDGE0_MEM_CTRL3

0x10c - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.

sec_ctrl_apb_bridge1_mem_ctrl0: SEC_CTRL_APB_BRIDGE1_MEM_CTRL0

0x110 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.

sec_ctrl_apb_bridge1_mem_ctrl1: SEC_CTRL_APB_BRIDGE1_MEM_CTRL1

0x114 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.

sec_ctrl_apb_bridge1_mem_ctrl2: SEC_CTRL_APB_BRIDGE1_MEM_CTRL2

0x118 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.

sec_ctrl_apb_bridge1_mem_ctrl3: SEC_CTRL_APB_BRIDGE1_MEM_CTRL3

0x11c - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.

sec_ctrl_ahb0_0_slave_rule: SEC_CTRL_AHB0_0_SLAVE_RULE

0x120 - Security access rules for AHB peripherals.

sec_ctrl_ahb0_1_slave_rule: SEC_CTRL_AHB0_1_SLAVE_RULE

0x124 - Security access rules for AHB peripherals.

sec_ctrl_ahb1_0_slave_rule: SEC_CTRL_AHB1_0_SLAVE_RULE

0x130 - Security access rules for AHB peripherals.

sec_ctrl_ahb1_1_slave_rule: SEC_CTRL_AHB1_1_SLAVE_RULE

0x134 - Security access rules for AHB peripherals.

sec_ctrl_ahb2_0_slave_rule: SEC_CTRL_AHB2_0_SLAVE_RULE

0x140 - Security access rules for AHB peripherals.

sec_ctrl_ahb2_1_slave_rule: SEC_CTRL_AHB2_1_SLAVE_RULE

0x144 - Security access rules for AHB peripherals.

sec_ctrl_ahb2_0_mem_rule: SEC_CTRL_AHB2_0_MEM_RULE

0x150 - Security access rules for AHB_SEC_CTRL_AHB.

sec_ctrl_usb_hs_slave_rule: SEC_CTRL_USB_HS_SLAVE_RULE

0x160 - Security access rules for USB High speed RAM slaves.

sec_ctrl_usb_hs_mem_rule: SEC_CTRL_USB_HS_MEM_RULE

0x170 - Security access rules for RAM_USB_HS.

sec_vio_addr: [SEC_VIO_ADDR; 12]

0xe00 - most recent security violation address for AHB layer n

sec_vio_misc_info: [SEC_VIO_MISC_INFO; 12]

0xe80 - most recent security violation miscellaneous information for AHB layer n

sec_vio_info_valid: SEC_VIO_INFO_VALID

0xf00 - security violation address/information registers valid flags

sec_gpio_mask0: SEC_GPIO_MASK0

0xf80 - Secure GPIO mask for port 0 pins.

sec_gpio_mask1: SEC_GPIO_MASK1

0xf84 - Secure GPIO mask for port 1 pins.

sec_cpu_int_mask0: SEC_CPU_INT_MASK0

0xf90 - Secure Interrupt mask for CPU1

sec_cpu_int_mask1: SEC_CPU_INT_MASK1

0xf94 - Secure Interrupt mask for CPU1

sec_mask_lock: SEC_MASK_LOCK

0xfbc - Security General Purpose register access control.

master_sec_level: MASTER_SEC_LEVEL

0xfd0 - master secure level register

master_sec_anti_pol_reg: MASTER_SEC_ANTI_POL_REG

0xfd4 - master secure level anti-pole register

cm33_lock_reg: CM33_LOCK_REG

0xfec - Miscalleneous control signals for in CM33 (CPU0)

mcm33_lock_reg: MCM33_LOCK_REG

0xff0 - Miscalleneous control signals for in micro-CM33 (CPU1)

misc_ctrl_dp_reg: MISC_CTRL_DP_REG

0xff8 - secure control duplicate register

misc_ctrl_reg: MISC_CTRL_REG

0xffc - secure control register

Auto Trait Implementations

Blanket Implementations

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T> From<T> for T[src]

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Same<T> for T

type Output = T

Should always be Self