crate::wrap_always_on_peripheral!(Syscon, SYSCON);
impl Syscon {
pub fn rev_id(&self) -> u8 {
self.raw.dieid.read().rev_id().bits()
}
}
impl Syscon {
pub fn enable_clock<P: ClockControl>(&mut self, peripheral: &mut P) {
peripheral.enable_clock(self);
}
pub fn disable_clock<P: ClockControl>(&mut self, peripheral: &mut P) {
peripheral.disable_clock(self);
}
pub fn is_clock_enabled<P: ClockControl>(&self, peripheral: &P) -> bool {
peripheral.is_clock_enabled(&self)
}
pub fn reset<P: ResetControl>(&mut self, peripheral: &mut P) {
peripheral.assert_reset(self);
peripheral.clear_reset(self);
}
}
impl Syscon {
}
pub trait ClockControl {
fn enable_clock(&self, s: &mut Syscon);
fn disable_clock(&self, s: &mut Syscon);
fn is_clock_enabled(&self, s: &Syscon) -> bool;
}
macro_rules! impl_clock_control {
($clock_control:ty, $clock:ident, $register:ident) => {
impl ClockControl for $clock_control {
fn enable_clock(&self, s: &mut Syscon) {
s.raw.$register.modify(|_, w| w.$clock().enable());
while s.raw.$register.read().$clock().is_disable() {}
}
fn disable_clock(&self, s: &mut Syscon) {
s.raw.$register.modify(|_, w| w.$clock().disable());
}
fn is_clock_enabled(&self, s: &Syscon) -> bool {
s.raw.$register.read().$clock().is_enable()
}
}
};
}
impl_clock_control!(raw::ADC0, adc, ahbclkctrl0);
impl_clock_control!(raw::FLASH, flash, ahbclkctrl0);
impl_clock_control!(raw::FLEXCOMM0, fc0, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM1, fc1, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM2, fc2, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM3, fc3, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM4, fc4, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM5, fc5, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM6, fc6, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM7, fc7, ahbclkctrl1);
impl_clock_control!(raw::FLEXCOMM8, hs_lspi, ahbclkctrl2);
impl_clock_control!(raw::IOCON, iocon, ahbclkctrl0);
impl_clock_control!(raw::GINT0, gint, ahbclkctrl0);
impl_clock_control!(raw::PINT, pint, ahbclkctrl0);
impl_clock_control!(raw::USB0, usb0_dev, ahbclkctrl1);
impl_clock_control!(raw::USBFSH, usb0_hosts, ahbclkctrl2); impl_clock_control!(raw::UTICK0, utick, ahbclkctrl1);
impl_clock_control!(raw::ANACTRL, analog_ctrl, ahbclkctrl2);
impl_clock_control!(raw::CASPER, casper, ahbclkctrl2);
impl_clock_control!(raw::PUF, puf, ahbclkctrl2);
impl_clock_control!(raw::RNG, rng, ahbclkctrl2);
impl ClockControl for raw::GPIO {
fn enable_clock(&self, s: &mut Syscon) {
s.raw.ahbclkctrl0.modify(|_, w| w.gpio0().enable());
s.raw.ahbclkctrl0.modify(|_, w| w.gpio1().enable());
}
fn disable_clock(&self, s: &mut Syscon) {
s.raw.ahbclkctrl0.modify(|_, w| w.gpio0().disable());
s.raw.ahbclkctrl0.modify(|_, w| w.gpio1().disable());
}
#[allow(clippy::nonminimal_bool)]
fn is_clock_enabled(&self, s: &Syscon) -> bool {
s.raw.ahbclkctrl0.read().gpio0().is_enable() && s.raw.ahbclkctrl0.read().gpio1().is_enable()
}
}
pub trait ResetControl {
fn assert_reset(&self, syscon: &mut Syscon);
fn clear_reset(&self, syscon: &mut Syscon);
}
macro_rules! impl_reset_control {
($reset_control:ty, $field:ident, $register:ident) => {
impl<'a> ResetControl for $reset_control {
fn assert_reset(&self, syscon: &mut Syscon) {
syscon.raw.$register.modify(|_, w| w.$field().asserted());
while syscon.raw.$register.read().$field().is_released() {}
}
fn clear_reset(&self, syscon: &mut Syscon) {
syscon.raw.$register.modify(|_, w| w.$field().released());
while syscon.raw.$register.read().$field().is_asserted() {}
}
}
};
($reset_control:ty, $field1:ident, $field2:ident, $register:ident) => {
impl<'a> ResetControl for $reset_control {
fn assert_reset(&self, syscon: &mut Syscon) {
syscon.raw.$register.modify(|_, w| w.$field1().asserted());
while syscon.raw.$register.read().$field1().is_released() {}
syscon.raw.$register.modify(|_, w| w.$field2().asserted());
while syscon.raw.$register.read().$field2().is_released() {}
}
fn clear_reset(&self, syscon: &mut Syscon) {
syscon.raw.$register.modify(|_, w| w.$field1().released());
while syscon.raw.$register.read().$field1().is_asserted() {}
syscon.raw.$register.modify(|_, w| w.$field2().released());
while syscon.raw.$register.read().$field2().is_asserted() {}
}
}
};
}
impl_reset_control!(raw::CASPER, casper_rst, presetctrl2);
impl_reset_control!(raw::FLEXCOMM0, fc0_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM1, fc1_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM2, fc2_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM3, fc3_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM4, fc4_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM5, fc5_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM6, fc6_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM7, fc7_rst, presetctrl1);
impl_reset_control!(raw::FLEXCOMM8, hs_lspi_rst, presetctrl2);
impl_reset_control!(raw::USB0, usb0_dev_rst, presetctrl1);
impl_reset_control!(raw::UTICK0, utick_rst, presetctrl1);
impl_reset_control!(raw::USBFSH, usb0_hostm_rst, usb0_hosts_rst, presetctrl2);