#[repr(C)]
pub struct RegisterBlock {
Show 16 fields pub enc_enable: Reg<ENC_ENABLE_SPEC>, pub mask_lsb: Reg<MASK_LSB_SPEC>, pub mask_msb: Reg<MASK_MSB_SPEC>, pub lock: Reg<LOCK_SPEC>, pub iv_lsb0: Reg<IV_LSB0_SPEC>, pub iv_msb0: Reg<IV_MSB0_SPEC>, pub base_addr0: Reg<BASE_ADDR0_SPEC>, pub sr_enable0: Reg<SR_ENABLE0_SPEC>, pub iv_lsb1: Reg<IV_LSB1_SPEC>, pub iv_msb1: Reg<IV_MSB1_SPEC>, pub base_addr1: Reg<BASE_ADDR1_SPEC>, pub sr_enable1: Reg<SR_ENABLE1_SPEC>, pub iv_lsb2: Reg<IV_LSB2_SPEC>, pub iv_msb2: Reg<IV_MSB2_SPEC>, pub base_addr2: Reg<BASE_ADDR2_SPEC>, pub sr_enable2: Reg<SR_ENABLE2_SPEC>,
}
Expand description

Register block

Fields

enc_enable: Reg<ENC_ENABLE_SPEC>

0x00 - Encryption Enable register

mask_lsb: Reg<MASK_LSB_SPEC>

0x04 - Data Mask register, 32 Least Significant Bits

mask_msb: Reg<MASK_MSB_SPEC>

0x08 - Data Mask register, 32 Most Significant Bits

lock: Reg<LOCK_SPEC>

0x0c - Lock register

iv_lsb0: Reg<IV_LSB0_SPEC>

0x10 - Initial Vector register for region 0, Least Significant Bits

iv_msb0: Reg<IV_MSB0_SPEC>

0x14 - Initial Vector register for region 0, Most Significant Bits

base_addr0: Reg<BASE_ADDR0_SPEC>

0x18 - Base Address for region 0 register

sr_enable0: Reg<SR_ENABLE0_SPEC>

0x1c - Sub-Region Enable register for region 0

iv_lsb1: Reg<IV_LSB1_SPEC>

0x20 - Initial Vector register for region 1, Least Significant Bits

iv_msb1: Reg<IV_MSB1_SPEC>

0x24 - Initial Vector register for region 1, Most Significant Bits

base_addr1: Reg<BASE_ADDR1_SPEC>

0x28 - Base Address for region 1 register

sr_enable1: Reg<SR_ENABLE1_SPEC>

0x2c - Sub-Region Enable register for region 1

iv_lsb2: Reg<IV_LSB2_SPEC>

0x30 - Initial Vector register for region 2, Least Significant Bits

iv_msb2: Reg<IV_MSB2_SPEC>

0x34 - Initial Vector register for region 2, Most Significant Bits

base_addr2: Reg<BASE_ADDR2_SPEC>

0x38 - Base Address for region 2 register

sr_enable2: Reg<SR_ENABLE2_SPEC>

0x3c - Sub-Region Enable register for region 2

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