pub enum ONECHANNEL_A {
    DUAL_CHANNEL,
    SINGLE_CHANNEL,
}
Expand description

Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.

Value on reset: 0

Variants

DUAL_CHANNEL

0: I2S data for this channel pair is treated as left and right channels.

SINGLE_CHANNEL

1: I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION.

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