Struct lpc55_pac::i2s0::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {}Show fields
pub cfg1: Reg<CFG1_SPEC>, pub cfg2: Reg<CFG2_SPEC>, pub stat: Reg<STAT_SPEC>, pub div: Reg<DIV_SPEC>, pub fifocfg: Reg<FIFOCFG_SPEC>, pub fifostat: Reg<FIFOSTAT_SPEC>, pub fifotrig: Reg<FIFOTRIG_SPEC>, pub fifointenset: Reg<FIFOINTENSET_SPEC>, pub fifointenclr: Reg<FIFOINTENCLR_SPEC>, pub fifointstat: Reg<FIFOINTSTAT_SPEC>, pub fifowr: Reg<FIFOWR_SPEC>, pub fifowr48h: Reg<FIFOWR48H_SPEC>, pub fiford: Reg<FIFORD_SPEC>, pub fiford48h: Reg<FIFORD48H_SPEC>, pub fifordnopop: Reg<FIFORDNOPOP_SPEC>, pub fiford48hnopop: Reg<FIFORD48HNOPOP_SPEC>, pub id: Reg<ID_SPEC>, // some fields omitted
Register block
Fields
cfg1: Reg<CFG1_SPEC>0xc00 - Configuration register 1 for the primary channel pair.
cfg2: Reg<CFG2_SPEC>0xc04 - Configuration register 2 for the primary channel pair.
stat: Reg<STAT_SPEC>0xc08 - Status register for the primary channel pair.
div: Reg<DIV_SPEC>0xc1c - Clock divider, used by all channel pairs.
fifocfg: Reg<FIFOCFG_SPEC>0xe00 - FIFO configuration and enable register.
fifostat: Reg<FIFOSTAT_SPEC>0xe04 - FIFO status register.
fifotrig: Reg<FIFOTRIG_SPEC>0xe08 - FIFO trigger settings for interrupt and DMA request.
fifointenset: Reg<FIFOINTENSET_SPEC>0xe10 - FIFO interrupt enable set (enable) and read register.
fifointenclr: Reg<FIFOINTENCLR_SPEC>0xe14 - FIFO interrupt enable clear (disable) and read register.
fifointstat: Reg<FIFOINTSTAT_SPEC>0xe18 - FIFO interrupt status register.
fifowr: Reg<FIFOWR_SPEC>0xe20 - FIFO write data.
fifowr48h: Reg<FIFOWR48H_SPEC>0xe24 - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fiford: Reg<FIFORD_SPEC>0xe30 - FIFO read data.
fiford48h: Reg<FIFORD48H_SPEC>0xe34 - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fifordnopop: Reg<FIFORDNOPOP_SPEC>0xe40 - FIFO data read with no FIFO pop.
fiford48hnopop: Reg<FIFORD48HNOPOP_SPEC>0xe44 - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
id: Reg<ID_SPEC>0xffc - I2S Module identification