[−][src]Module lpc54606_pac::system_control::ccr

Configuration and Control Register

Structs

BFHFNMIGN_W	Write proxy for field `BFHFNMIGN`
DIV_0_TRP_W	Write proxy for field `DIV_0_TRP`
NONBASETHRDENA_W	Write proxy for field `NONBASETHRDENA`
STKALIGN_W	Write proxy for field `STKALIGN`
UNALIGN_TRP_W	Write proxy for field `UNALIGN_TRP`
USERSETMPEND_W	Write proxy for field `USERSETMPEND`

BFHFNMIGN_A	Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
DIV_0_TRP_A	Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
NONBASETHRDENA_A	no description available
STKALIGN_A	Indicates stack alignment on exception entry
UNALIGN_TRP_A	Enables unaligned access traps
USERSETMPEND_A	Enables unprivileged software access to the STIR

BFHFNMIGN_R	Reader of field `BFHFNMIGN`
DIV_0_TRP_R	Reader of field `DIV_0_TRP`
NONBASETHRDENA_R	Reader of field `NONBASETHRDENA`
R	Reader of register CCR
STKALIGN_R	Reader of field `STKALIGN`
UNALIGN_TRP_R	Reader of field `UNALIGN_TRP`
USERSETMPEND_R	Reader of field `USERSETMPEND`
W	Writer for register CCR