Type Definition lpc54606_pac::spifi0::ctrl::R

type R = R<u32, CTRL>;

Reader of register CTRL

Methods

impl R

pub fn timeout(&self) -> TIMEOUT_R

Bits 0:15 - This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again.

pub fn cshigh(&self) -> CSHIGH_R

Bits 16:19 - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.

pub fn d_prftch_dis(&self) -> D_PRFTCH_DIS_R

Bit 21 - This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses.

pub fn inten(&self) -> INTEN_R

Bit 22 - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details.

pub fn mode3(&self) -> MODE3_R

Bit 23 - SPI Mode 3 select.

pub fn prftch_dis(&self) -> PRFTCH_DIS_R

Bit 27 - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.

pub fn dual(&self) -> DUAL_R

Bit 28 - Select dual protocol.

pub fn rfclk(&self) -> RFCLK_R

Bit 29 - Select active clock edge for input data.

pub fn fbclk(&self) -> FBCLK_R

Bit 30 - Feedback clock select.

pub fn dmaen(&self) -> DMAEN_R

Bit 31 - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode.