Enum lpc54606_pac::spifi0::ctrl::RFCLK_A

pub enum RFCLK_A {
    RISING_EDGE,
    FALLING_EDGE,
}

Select active clock edge for input data.

Value on reset: 0

Variants

RISING_EDGE

0: Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.

FALLING_EDGE

1: Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.

Trait Implementations

impl Clone for RFCLK_A

fn clone(&self) -> RFCLK_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for RFCLK_A

impl Debug for RFCLK_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<RFCLK_A> for bool

fn from(variant: RFCLK_A) -> Self

Performs the conversion.

impl PartialEq<RFCLK_A> for RFCLK_A

fn eq(&self, other: &RFCLK_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for RFCLK_A