[][src]Type Definition lpc54606_pac::spifi0::cmd::R

type R = R<u32, CMD>;

Reader of register CMD

Methods

impl R[src]

pub fn datalen(&self) -> DATALEN_R[src]

Bits 0:13 - Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field.

pub fn poll(&self) -> POLL_R[src]

Bit 14 - This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs

pub fn dout(&self) -> DOUT_R[src]

Bit 15 - If the DATALEN field is not zero, this bit controls the direction of the data:

pub fn intlen(&self) -> INTLEN_R[src]

Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.

pub fn fieldform(&self) -> FIELDFORM_R[src]

Bits 19:20 - This field controls how the fields of the command are sent.

pub fn frameform(&self) -> FRAMEFORM_R[src]

Bits 21:23 - This field controls the opcode and address fields.

pub fn opcode(&self) -> OPCODE_R[src]

Bits 24:31 - The opcode of the command (not used for some FRAMEFORM values).