Type Definition lpc54606_pac::spi0::fifocfg::W

type W = W<u32, FIFOCFG>;

Writer for register FIFOCFG

Methods

impl W

pub fn enabletx(&mut self) -> ENABLETX_W

Bit 0 - Enable the transmit FIFO.

pub fn enablerx(&mut self) -> ENABLERX_W

Bit 1 - Enable the receive FIFO.

pub fn dmatx(&mut self) -> DMATX_W

Bit 12 - DMA configuration for transmit.

pub fn dmarx(&mut self) -> DMARX_W

Bit 13 - DMA configuration for receive.

pub fn waketx(&mut self) -> WAKETX_W

Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

pub fn wakerx(&mut self) -> WAKERX_W

Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

pub fn emptytx(&mut self) -> EMPTYTX_W

Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.

pub fn emptyrx(&mut self) -> EMPTYRX_W

Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.

pub fn popdbg(&mut self) -> POPDBG_W

Bit 18 - Pop FIFO for debug reads.