[][src]Type Definition lpc54606_pac::sct0::dmareq0::W

type W = W<u32, DMAREQ0>;

Writer for register DMAREQ0

Methods

impl W[src]

pub fn dev_0(&mut self) -> DEV_0_W[src]

Bits 0:15 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

pub fn drl0(&mut self) -> DRL0_W[src]

Bit 30 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.

pub fn drq0(&mut self) -> DRQ0_W[src]

Bit 31 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.