[−][src]Module lpc54606_pac::i2s0::fifocfg

FIFO configuration and enable register.

Structs

DMARX_W	Write proxy for field `DMARX`
DMATX_W	Write proxy for field `DMATX`
EMPTYRX_W	Write proxy for field `EMPTYRX`
EMPTYTX_W	Write proxy for field `EMPTYTX`
ENABLERX_W	Write proxy for field `ENABLERX`
ENABLETX_W	Write proxy for field `ENABLETX`
PACK48_W	Write proxy for field `PACK48`
POPDBG_W	Write proxy for field `POPDBG`
TXI2SE0_W	Write proxy for field `TXI2SE0`
WAKERX_W	Write proxy for field `WAKERX`
WAKETX_W	Write proxy for field `WAKETX`

DMARX_A	DMA configuration for receive.
DMATX_A	DMA configuration for transmit.
ENABLERX_A	Enable the receive FIFO.
ENABLETX_A	Enable the transmit FIFO.
PACK48_A	Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
POPDBG_A	Pop FIFO for debug reads.
TXI2SE0_A	Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.
WAKERX_A	Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
WAKETX_A	Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.