Type Definition lpc54606_pac::enet::mtl_op_mode::W

type W = W<u32, MTL_OP_MODE>;

Writer for register MTL_OP_MODE

Methods

impl W

pub fn dtxsts(&mut self) -> DTXSTS_W

Bit 1 - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.

pub fn schalg(&mut self) -> SCHALG_W

Bits 5:6 - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.

pub fn cntprst(&mut self) -> CNTPRST_W

Bit 8 - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.

pub fn cntclr(&mut self) -> CNTCLR_W

Bit 9 - Counters Reset When this bit is set, all counters are reset.