Type Definition lpc54606_pac::enet::mac_rxtx_stat::R

type R = R<u32, MAC_RXTX_STAT>;

Reader of register MAC_RXTX_STAT

Methods

impl R

pub fn tjt(&self) -> TJT_R

Bit 0 - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.

pub fn ncarr(&self) -> NCARR_R

Bit 1 - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission.

pub fn lcarr(&self) -> LCARR_R

Bit 2 - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the loss of carrier occurred during packet transmission, that is, the PHY Carrier signal was inactive for one or more transmission clock periods during packet transmission.

pub fn exdef(&self) -> EXDEF_R

Bit 3 - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when Jumbo packet is enabled).

pub fn lcol(&self) -> LCOL_R

Bit 4 - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode).

pub fn excol(&self) -> EXCOL_R

Bit 5 - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet.

pub fn rwt(&self) -> RWT_R

Bit 8 - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC Configuration register Table 722.