Type Definition lpc54606_pac::enet::dma_ch::dma_chx_stat::W

type W = W<u32, DMA_CHX_STAT>;

Writer for register DMA_CHx_STAT

Methods

impl W

pub fn ti(&mut self) -> TI_W

Bit 0 - Transmit Interrupt This bit indicates that the packet transmission is complete.

pub fn tps(&mut self) -> TPS_W

Bit 1 - Transmit Process Stopped This bit is set when the transmission is stopped.

pub fn tbu(&mut self) -> TBU_W

Bit 2 - Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list, and the DMA cannot acquire it.

pub fn ri(&mut self) -> RI_W

Bit 6 - Receive Interrupt This bit indicates that the packet reception is complete.

pub fn rbu(&mut self) -> RBU_W

Bit 7 - Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list, and the DMA cannot acquire it.

pub fn rps(&mut self) -> RPS_W

Bit 8 - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.

pub fn rwt(&mut self) -> RWT_W

Bit 9 - Receive Watchdog time out This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.

pub fn eti(&mut self) -> ETI_W

Bit 10 - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.

pub fn eri(&mut self) -> ERI_W

Bit 11 - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.

pub fn fbe(&mut self) -> FBE_W

Bit 12 - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).

pub fn ais(&mut self) -> AIS_W

Bit 14 - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit.

pub fn nis(&mut self) -> NIS_W

Bit 15 - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal Interrupt Summary bit.

pub fn eb(&mut self) -> EB_W

Bits 16:18 - DMA Error Bits This field indicates the type of error that caused a Bus Error.