[][src]Type Definition lpc54606_pac::enet::dma_ch::dma_chx_int_en::W

type W = W<u32, DMA_CHX_INT_EN>;

Writer for register DMA_CHx_INT_EN

Methods

impl W[src]

pub fn tie(&mut self) -> TIE_W[src]

Bit 0 - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled.

pub fn tse(&mut self) -> TSE_W[src]

Bit 1 - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled.

pub fn tbue(&mut self) -> TBUE_W[src]

Bit 2 - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.

pub fn rie(&mut self) -> RIE_W[src]

Bit 6 - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled.

pub fn rbue(&mut self) -> RBUE_W[src]

Bit 7 - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.

pub fn rse(&mut self) -> RSE_W[src]

Bit 8 - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled.

pub fn rwte(&mut self) -> RWTE_W[src]

Bit 9 - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.

pub fn etie(&mut self) -> ETIE_W[src]

Bit 10 - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled.

pub fn erie(&mut self) -> ERIE_W[src]

Bit 11 - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled.

pub fn fbee(&mut self) -> FBEE_W[src]

Bit 12 - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled.

pub fn aie(&mut self) -> AIE_W[src]

Bit 14 - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.

pub fn nie(&mut self) -> NIE_W[src]

Bit 15 - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.