Type Definition lpc54606_pac::dmic0::channel::fifo_ctrl::W

type W = W<u32, FIFO_CTRL>;

Writer for register FIFO_CTRL

Methods

impl W

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - FIFO enable.

pub fn resetn(&mut self) -> RESETN_W

Bit 1 - FIFO reset.

pub fn inten(&mut self) -> INTEN_W

Bit 2 - Interrupt enable.

pub fn dmaen(&mut self) -> DMAEN_W

Bit 3 - DMA enable

pub fn triglvl(&mut self) -> TRIGLVL_W

Bits 16:20 - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).