Type Definition lpc54606_pac::dmic0::channel::fifo_ctrl::R

type R = R<u32, FIFO_CTRL>;

Reader of register FIFO_CTRL

Methods

impl R

pub fn enable(&self) -> ENABLE_R

Bit 0 - FIFO enable.

pub fn resetn(&self) -> RESETN_R

Bit 1 - FIFO reset.

pub fn inten(&self) -> INTEN_R

Bit 2 - Interrupt enable.

pub fn dmaen(&self) -> DMAEN_R

Bit 3 - DMA enable

pub fn triglvl(&self) -> TRIGLVL_R

Bits 16:20 - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).