[][src]Enum lpc54606_pac::dma0::channel::cfg::DSTBURSTWRAP_A

pub enum DSTBURSTWRAP_A {
    DISABLED,
    ENABLED,
}

Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.

Value on reset: 0

Variants

DISABLED

0: Disabled. Destination burst wrapping is not enabled for this DMA channel.

ENABLED

1: Enabled. Destination burst wrapping is enabled for this DMA channel.

Trait Implementations

impl Clone for DSTBURSTWRAP_A[src]

impl Copy for DSTBURSTWRAP_A[src]

impl Debug for DSTBURSTWRAP_A[src]

impl From<DSTBURSTWRAP_A> for bool[src]

impl PartialEq<DSTBURSTWRAP_A> for DSTBURSTWRAP_A[src]

impl StructuralPartialEq for DSTBURSTWRAP_A[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T> Same<T> for T

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.