[][src]Type Definition lpc54606_pac::ctimer0::ccr::R

type R = R<u32, CCR>;

Reader of register CCR

Methods

impl R[src]

pub fn cap0re(&self) -> CAP0RE_R[src]

Bit 0 - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap0fe(&self) -> CAP0FE_R[src]

Bit 1 - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap0i(&self) -> CAP0I_R[src]

Bit 2 - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.

pub fn cap1re(&self) -> CAP1RE_R[src]

Bit 3 - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap1fe(&self) -> CAP1FE_R[src]

Bit 4 - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap1i(&self) -> CAP1I_R[src]

Bit 5 - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.

pub fn cap2re(&self) -> CAP2RE_R[src]

Bit 6 - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap2fe(&self) -> CAP2FE_R[src]

Bit 7 - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap2i(&self) -> CAP2I_R[src]

Bit 8 - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.

pub fn cap3re(&self) -> CAP3RE_R[src]

Bit 9 - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap3fe(&self) -> CAP3FE_R[src]

Bit 10 - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

pub fn cap3i(&self) -> CAP3I_R[src]

Bit 11 - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.