[−][src]Struct lpc54606_pac::adc0::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub insel: INSEL,
    pub seq_ctrla: SEQ_CTRL,
    pub seq_ctrlb: SEQ_CTRL,
    pub seq_gdata: SEQ_GDAT,
    pub seq_gdatb: SEQ_GDAT,
    pub dat: [DAT; 12],
    pub thr0_low: THR0_LOW,
    pub thr1_low: THR1_LOW,
    pub thr0_high: THR0_HIGH,
    pub thr1_high: THR1_HIGH,
    pub chan_thrsel: CHAN_THRSEL,
    pub inten: INTEN,
    pub flags: FLAGS,
    pub startup: STARTUP,
    pub calib: CALIB,
    // some fields omitted
}

Register block

Fields

ctrl: CTRL

0x00 - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.

insel: INSEL

0x04 - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0.

seq_ctrla: SEQ_CTRL

0x08 - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.

seq_ctrlb: SEQ_CTRL

0x0c - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.

seq_gdata: SEQ_GDAT

0x10 - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.

seq_gdatb: SEQ_GDAT

0x14 - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.

dat: [DAT; 12]

0x20 - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0.

thr0_low: THR0_LOW

0x50 - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.

thr1_low: THR1_LOW

0x54 - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.

thr0_high: THR0_HIGH

0x58 - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.

thr1_high: THR1_HIGH

0x5c - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.

chan_thrsel: CHAN_THRSEL

0x60 - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel

inten: INTEN

0x64 - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.

flags: FLAGS

0x68 - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).

startup: STARTUP

0x6c - ADC Startup register.

calib: CALIB

0x70 - ADC Calibration register.

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