[][src]Enum lpc54606_pac::adc0::seq_ctrl::SEQ_ENA_A

pub enum SEQ_ENA_A {
    DISABLED,
    ENABLED,
}

Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.

Value on reset: 0

Variants

DISABLED

0: Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.

ENABLED

1: Enabled. Sequence n is enabled.

Trait Implementations

impl Clone for SEQ_ENA_A[src]

impl Copy for SEQ_ENA_A[src]

impl Debug for SEQ_ENA_A[src]

impl From<SEQ_ENA_A> for bool[src]

impl PartialEq<SEQ_ENA_A> for SEQ_ENA_A[src]

impl StructuralPartialEq for SEQ_ENA_A[src]

Auto Trait Implementations

impl Send for SEQ_ENA_A

impl Sync for SEQ_ENA_A

impl Unpin for SEQ_ENA_A

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Same<T> for T

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.