Type Definition lpc54606_pac::adc0::flags::R

type R = R<u32, FLAGS>;

Reader of register FLAGS

Methods

impl R

pub fn thcmp0(&self) -> THCMP0_R

Bit 0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.

pub fn thcmp1(&self) -> THCMP1_R

Bit 1 - Threshold comparison event on Channel 1. See description for channel 0.

pub fn thcmp2(&self) -> THCMP2_R

Bit 2 - Threshold comparison event on Channel 2. See description for channel 0.

pub fn thcmp3(&self) -> THCMP3_R

Bit 3 - Threshold comparison event on Channel 3. See description for channel 0.

pub fn thcmp4(&self) -> THCMP4_R

Bit 4 - Threshold comparison event on Channel 4. See description for channel 0.

pub fn thcmp5(&self) -> THCMP5_R

Bit 5 - Threshold comparison event on Channel 5. See description for channel 0.

pub fn thcmp6(&self) -> THCMP6_R

Bit 6 - Threshold comparison event on Channel 6. See description for channel 0.

pub fn thcmp7(&self) -> THCMP7_R

Bit 7 - Threshold comparison event on Channel 7. See description for channel 0.

pub fn thcmp8(&self) -> THCMP8_R

Bit 8 - Threshold comparison event on Channel 8. See description for channel 0.

pub fn thcmp9(&self) -> THCMP9_R

Bit 9 - Threshold comparison event on Channel 9. See description for channel 0.

pub fn thcmp10(&self) -> THCMP10_R

Bit 10 - Threshold comparison event on Channel 10. See description for channel 0.

pub fn thcmp11(&self) -> THCMP11_R

Bit 11 - Threshold comparison event on Channel 11. See description for channel 0.

pub fn overrun0(&self) -> OVERRUN0_R

Bit 12 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0

pub fn overrun1(&self) -> OVERRUN1_R

Bit 13 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1

pub fn overrun2(&self) -> OVERRUN2_R

Bit 14 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2

pub fn overrun3(&self) -> OVERRUN3_R

Bit 15 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3

pub fn overrun4(&self) -> OVERRUN4_R

Bit 16 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4

pub fn overrun5(&self) -> OVERRUN5_R

Bit 17 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5

pub fn overrun6(&self) -> OVERRUN6_R

Bit 18 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6

pub fn overrun7(&self) -> OVERRUN7_R

Bit 19 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7

pub fn overrun8(&self) -> OVERRUN8_R

Bit 20 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8

pub fn overrun9(&self) -> OVERRUN9_R

Bit 21 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9

pub fn overrun10(&self) -> OVERRUN10_R

Bit 22 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10

pub fn overrun11(&self) -> OVERRUN11_R

Bit 23 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11

pub fn seqa_ovr(&self) -> SEQA_OVR_R

Bit 24 - Mirrors the global OVERRUN status flag in the SEQA_GDAT register

pub fn seqb_ovr(&self) -> SEQB_OVR_R

Bit 25 - Mirrors the global OVERRUN status flag in the SEQB_GDAT register

pub fn seqa_int(&self) -> SEQA_INT_R

Bit 28 - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.

pub fn seqb_int(&self) -> SEQB_INT_R

Bit 29 - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.

pub fn thcmp_int(&self) -> THCMP_INT_R

Bit 30 - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.

pub fn ovr_int(&self) -> OVR_INT_R

Bit 31 - Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.