[][src]Struct lpc54606_pac::dma0::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub intstat: INTSTAT,
    pub srambase: SRAMBASE,
    pub enableset0: ENABLESET0,
    pub enableclr0: ENABLECLR0,
    pub active0: ACTIVE0,
    pub busy0: BUSY0,
    pub errint0: ERRINT0,
    pub intenset0: INTENSET0,
    pub intenclr0: INTENCLR0,
    pub inta0: INTA0,
    pub intb0: INTB0,
    pub setvalid0: SETVALID0,
    pub settrig0: SETTRIG0,
    pub abort0: ABORT0,
    pub channel0: CHANNEL,
    pub channel1: CHANNEL,
    pub channel2: CHANNEL,
    pub channel3: CHANNEL,
    pub channel4: CHANNEL,
    pub channel5: CHANNEL,
    pub channel6: CHANNEL,
    pub channel7: CHANNEL,
    pub channel8: CHANNEL,
    pub channel9: CHANNEL,
    pub channel10: CHANNEL,
    pub channel11: CHANNEL,
    pub channel12: CHANNEL,
    pub channel13: CHANNEL,
    pub channel14: CHANNEL,
    pub channel15: CHANNEL,
    pub channel16: CHANNEL,
    pub channel17: CHANNEL,
    pub channel18: CHANNEL,
    pub channel19: CHANNEL,
    pub channel20: CHANNEL,
    pub channel21: CHANNEL,
    pub channel22: CHANNEL,
    pub channel23: CHANNEL,
    pub channel24: CHANNEL,
    pub channel25: CHANNEL,
    pub channel26: CHANNEL,
    pub channel27: CHANNEL,
    pub channel28: CHANNEL,
    pub channel29: CHANNEL,
    // some fields omitted
}

Register block

Fields

ctrl: CTRL

0x00 - DMA control.

intstat: INTSTAT

0x04 - Interrupt status.

srambase: SRAMBASE

0x08 - SRAM address of the channel configuration table.

enableset0: ENABLESET0

0x20 - Channel Enable read and Set for all DMA channels.

enableclr0: ENABLECLR0

0x28 - Channel Enable Clear for all DMA channels.

active0: ACTIVE0

0x30 - Channel Active status for all DMA channels.

busy0: BUSY0

0x38 - Channel Busy status for all DMA channels.

errint0: ERRINT0

0x40 - Error Interrupt status for all DMA channels.

intenset0: INTENSET0

0x48 - Interrupt Enable read and Set for all DMA channels.

intenclr0: INTENCLR0

0x50 - Interrupt Enable Clear for all DMA channels.

inta0: INTA0

0x58 - Interrupt A status for all DMA channels.

intb0: INTB0

0x60 - Interrupt B status for all DMA channels.

setvalid0: SETVALID0

0x68 - Set ValidPending control bits for all DMA channels.

settrig0: SETTRIG0

0x70 - Set Trigger control bits for all DMA channels.

abort0: ABORT0

0x78 - Channel Abort control for all DMA channels.

channel0: CHANNEL

0x400 - no description available

channel1: CHANNEL

0x410 - no description available

channel2: CHANNEL

0x420 - no description available

channel3: CHANNEL

0x430 - no description available

channel4: CHANNEL

0x440 - no description available

channel5: CHANNEL

0x450 - no description available

channel6: CHANNEL

0x460 - no description available

channel7: CHANNEL

0x470 - no description available

channel8: CHANNEL

0x480 - no description available

channel9: CHANNEL

0x490 - no description available

channel10: CHANNEL

0x4a0 - no description available

channel11: CHANNEL

0x4b0 - no description available

channel12: CHANNEL

0x4c0 - no description available

channel13: CHANNEL

0x4d0 - no description available

channel14: CHANNEL

0x4e0 - no description available

channel15: CHANNEL

0x4f0 - no description available

channel16: CHANNEL

0x500 - no description available

channel17: CHANNEL

0x510 - no description available

channel18: CHANNEL

0x520 - no description available

channel19: CHANNEL

0x530 - no description available

channel20: CHANNEL

0x540 - no description available

channel21: CHANNEL

0x550 - no description available

channel22: CHANNEL

0x560 - no description available

channel23: CHANNEL

0x570 - no description available

channel24: CHANNEL

0x580 - no description available

channel25: CHANNEL

0x590 - no description available

channel26: CHANNEL

0x5a0 - no description available

channel27: CHANNEL

0x5b0 - no description available

channel28: CHANNEL

0x5c0 - no description available

channel29: CHANNEL

0x5d0 - no description available

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