Module lpc43xx::sdmmc
[−]
[src]
SD/MMC
Modules
| blksiz |
Block Size Register |
| bmod |
Bus Mode Register |
| bufaddr |
Current Buffer Descriptor Address Register |
| bytcnt |
Byte Count Register |
| cdetect |
Card Detect Register |
| clkdiv |
Clock Divider Register |
| clkena |
Clock Enable Register |
| clksrc |
SD Clock Source Register |
| cmd |
Command Register |
| cmdarg |
Command Argument Register |
| ctrl |
Control Register |
| ctype |
Card Type Register |
| dbaddr |
Descriptor List Base Address Register |
| debnce |
Debounce Count Register |
| dscaddr |
Current Host Descriptor Address Register |
| fifoth |
FIFO Threshold Watermark Register |
| idinten |
Internal DMAC Interrupt Enable Register |
| idsts |
Internal DMAC Status Register |
| intmask |
Interrupt Mask Register |
| mintsts |
Masked Interrupt Status Register |
| pldmnd |
Poll Demand Register |
| pwren |
Power Enable Register |
| resp0 |
Response Register 0 |
| resp1 |
Response Register 1 |
| resp2 |
Response Register 2 |
| resp3 |
Response Register 3 |
| rintsts |
Raw Interrupt Status Register |
| rst_n |
Hardware Reset |
| status |
Status Register |
| tbbcnt |
Transferred Host to BIU-FIFO Byte Count Register |
| tcbcnt |
Transferred CIU Card Byte Count Register |
| tmout |
Time-out Register |
| wrtprt |
Write Protect Register |
Structs
| BLKSIZ |
Block Size Register |
| BMOD |
Bus Mode Register |
| BUFADDR |
Current Buffer Descriptor Address Register |
| BYTCNT |
Byte Count Register |
| CDETECT |
Card Detect Register |
| CLKDIV |
Clock Divider Register |
| CLKENA |
Clock Enable Register |
| CLKSRC |
SD Clock Source Register |
| CMD |
Command Register |
| CMDARG |
Command Argument Register |
| CTRL |
Control Register |
| CTYPE |
Card Type Register |
| DBADDR |
Descriptor List Base Address Register |
| DEBNCE |
Debounce Count Register |
| DSCADDR |
Current Host Descriptor Address Register |
| FIFOTH |
FIFO Threshold Watermark Register |
| IDINTEN |
Internal DMAC Interrupt Enable Register |
| IDSTS |
Internal DMAC Status Register |
| INTMASK |
Interrupt Mask Register |
| MINTSTS |
Masked Interrupt Status Register |
| PLDMND |
Poll Demand Register |
| PWREN |
Power Enable Register |
| RESP0 |
Response Register 0 |
| RESP1 |
Response Register 1 |
| RESP2 |
Response Register 2 |
| RESP3 |
Response Register 3 |
| RINTSTS |
Raw Interrupt Status Register |
| RST_N |
Hardware Reset |
| RegisterBlock |
Register block |
| STATUS |
Status Register |
| TBBCNT |
Transferred Host to BIU-FIFO Byte Count Register |
| TCBCNT |
Transferred CIU Card Byte Count Register |
| TMOUT |
Time-out Register |
| WRTPRT |
Write Protect Register |