Struct lpc43xx::i2c0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub conset: CONSET,
    pub stat: STAT,
    pub dat: DAT,
    pub adr0: ADR0,
    pub sclh: SCLH,
    pub scll: SCLL,
    pub conclr: CONCLR,
    pub mmctrl: MMCTRL,
    pub adr1: ADR,
    pub adr2: ADR,
    pub adr3: ADR,
    pub data_buffer: DATA_BUFFER,
    pub mask: [MASK; 4],
}

Register block

Fields

conset: CONSET

0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.

stat: STAT

0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.

dat: DAT

0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.

adr0: ADR0

0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

sclh: SCLH

0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.

scll: SCLL

0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.

conclr: CONCLR

0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.

mmctrl: MMCTRL

0x1c - Monitor mode control register.

adr1: ADR

0x20 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

adr2: ADR

0x24 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

adr3: ADR

0x28 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

data_buffer: DATA_BUFFER

0x2c - Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.

mask: [MASK; 4]

0x30 - I2C Slave address mask register

Trait Implementations