Module lpc43xx::adchs

12-bit Analog-to-Digital Converter High-Speed (ADCHS)

Modules

adc_speed	ADC speed control
clr_en0	Interrupt 0 clear mask
clr_en1	Interrupt 1 mask clear enable.
clr_stat0	Interrupt 0 clear status
clr_stat1	Interrupt 1 clear status
config	Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down.
descriptor0	Table 0 descriptor n, n= 0 to 7
descriptor1	Table 1 descriptors n, n=0 to 7
dma_req	Set or clear DMA write request
dscr_sts	Indicates active descriptor table and descriptor entry
fifo_cfg	Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word.
fifo_output	FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples
fifo_sts	Indicates FIFO fill level status
flush	Flushes FIFO
last_sample	Contains last converted sample of input M [M=0..5) and result of window comparator.
mask0	Interrupt 0 mask
mask1	Interrupt 1 mask
power_control	Configures ADC power vs. speed, DC-in biasing, output format and power gating.
power_down	Set or clear power down mode
set_en0	Interrupt 0 set mask
set_en1	Interrupt 1 mask set enable
set_stat0	Interrupt 0 set status
set_stat1	Interrupt 1 set status
status0	Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow
status1	Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun.
thr_a	Configures window comparator A levels.
thr_b	Configures window comparator B levels.
trigger	Enable software trigger to start descriptor processing

Structs

ADC_SPEED	ADC speed control
CLR_EN0	Interrupt 0 clear mask
CLR_EN1	Interrupt 1 mask clear enable.
CLR_STAT0	Interrupt 0 clear status
CLR_STAT1	Interrupt 1 clear status
CONFIG	Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down.
DESCRIPTOR0	Table 0 descriptor n, n= 0 to 7
DESCRIPTOR1	Table 1 descriptors n, n=0 to 7
DMA_REQ	Set or clear DMA write request
DSCR_STS	Indicates active descriptor table and descriptor entry
FIFO_CFG	Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word.
FIFO_OUTPUT	FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples
FIFO_STS	Indicates FIFO fill level status
FLUSH	Flushes FIFO
LAST_SAMPLE	Contains last converted sample of input M [M=0..5) and result of window comparator.
MASK0	Interrupt 0 mask
MASK1	Interrupt 1 mask
POWER_CONTROL	Configures ADC power vs. speed, DC-in biasing, output format and power gating.
POWER_DOWN	Set or clear power down mode
RegisterBlock	Register block
SET_EN0	Interrupt 0 set mask
SET_EN1	Interrupt 1 mask set enable
SET_STAT0	Interrupt 0 set status
SET_STAT1	Interrupt 1 set status
STATUS0	Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow
STATUS1	Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun.
THR_A	Configures window comparator A levels.
THR_B	Configures window comparator B levels.
TRIGGER	Enable software trigger to start descriptor processing