Struct lpc177x_8x::gpdma::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock { pub intstat: INTSTAT, pub inttcstat: INTTCSTAT, pub inttcclear: INTTCCLEAR, pub interrstat: INTERRSTAT, pub interrclr: INTERRCLR, pub rawinttcstat: RAWINTTCSTAT, pub rawinterrstat: RAWINTERRSTAT, pub enbldchns: ENBLDCHNS, pub softbreq: SOFTBREQ, pub softsreq: SOFTSREQ, pub softlbreq: SOFTLBREQ, pub softlsreq: SOFTLSREQ, pub dma_config: DMA_CONFIG, pub sync: SYNC, pub srcaddr0: SRCADDR, pub destaddr0: DESTADDR, pub lli0: LLI, pub control0: CONTROL, pub config0: CONFIG, pub srcaddr1: SRCADDR, pub destaddr1: DESTADDR, pub lli1: LLI, pub control1: CONTROL, pub config1: CONFIG, pub srcaddr2: SRCADDR, pub destaddr2: DESTADDR, pub lli2: LLI, pub control2: CONTROL, pub config2: CONFIG, pub srcaddr3: SRCADDR, pub destaddr3: DESTADDR, pub lli3: LLI, pub control3: CONTROL, pub config3: CONFIG, pub srcaddr4: SRCADDR, pub destaddr4: DESTADDR, pub lli4: LLI, pub control4: CONTROL, pub config4: CONFIG, pub srcaddr5: SRCADDR, pub destaddr5: DESTADDR, pub lli5: LLI, pub control5: CONTROL, pub config5: CONFIG, pub srcaddr6: SRCADDR, pub destaddr6: DESTADDR, pub lli6: LLI, pub control6: CONTROL, pub config6: CONFIG, pub srcaddr7: SRCADDR, pub destaddr7: DESTADDR, pub lli7: LLI, pub control7: CONTROL, pub config7: CONFIG, // some fields omitted }
Register block
Fields
intstat: INTSTAT
0x00 - DMA Interrupt Status Register
inttcstat: INTTCSTAT
0x04 - DMA Interrupt Terminal Count Request Status Register
inttcclear: INTTCCLEAR
0x08 - DMA Interrupt Terminal Count Request Clear Register
interrstat: INTERRSTAT
0x0c - DMA Interrupt Error Status Register
interrclr: INTERRCLR
0x10 - DMA Interrupt Error Clear Register
rawinttcstat: RAWINTTCSTAT
0x14 - DMA Raw Interrupt Terminal Count Status Register
rawinterrstat: RAWINTERRSTAT
0x18 - DMA Raw Error Interrupt Status Register
enbldchns: ENBLDCHNS
0x1c - DMA Enabled Channel Register
softbreq: SOFTBREQ
0x20 - DMA Software Burst Request Register
softsreq: SOFTSREQ
0x24 - DMA Software Single Request Register
softlbreq: SOFTLBREQ
0x28 - DMA Software Last Burst Request Register
softlsreq: SOFTLSREQ
0x2c - DMA Software Last Single Request Register
dma_config: DMA_CONFIG
0x30 - DMA Configuration Register
sync: SYNC
0x34 - DMA Synchronization Register
srcaddr0: SRCADDR
0x100 - DMA Channel 0 Source Address Register
destaddr0: DESTADDR
0x104 - DMA Channel 0 Destination Address Register
lli0: LLI
0x108 - DMA Channel 0 Linked List Item Register
control0: CONTROL
0x10c - DMA Channel 0 Control Register
config0: CONFIG
0x110 - DMA Channel 0 Configuration Register[1]
srcaddr1: SRCADDR
0x120 - DMA Channel 0 Source Address Register
destaddr1: DESTADDR
0x124 - DMA Channel 0 Destination Address Register
lli1: LLI
0x128 - DMA Channel 0 Linked List Item Register
control1: CONTROL
0x12c - DMA Channel 0 Control Register
config1: CONFIG
0x130 - DMA Channel 0 Configuration Register[1]
srcaddr2: SRCADDR
0x140 - DMA Channel 0 Source Address Register
destaddr2: DESTADDR
0x144 - DMA Channel 0 Destination Address Register
lli2: LLI
0x148 - DMA Channel 0 Linked List Item Register
control2: CONTROL
0x14c - DMA Channel 0 Control Register
config2: CONFIG
0x150 - DMA Channel 0 Configuration Register[1]
srcaddr3: SRCADDR
0x160 - DMA Channel 0 Source Address Register
destaddr3: DESTADDR
0x164 - DMA Channel 0 Destination Address Register
lli3: LLI
0x168 - DMA Channel 0 Linked List Item Register
control3: CONTROL
0x16c - DMA Channel 0 Control Register
config3: CONFIG
0x170 - DMA Channel 0 Configuration Register[1]
srcaddr4: SRCADDR
0x180 - DMA Channel 0 Source Address Register
destaddr4: DESTADDR
0x184 - DMA Channel 0 Destination Address Register
lli4: LLI
0x188 - DMA Channel 0 Linked List Item Register
control4: CONTROL
0x18c - DMA Channel 0 Control Register
config4: CONFIG
0x190 - DMA Channel 0 Configuration Register[1]
srcaddr5: SRCADDR
0x1a0 - DMA Channel 0 Source Address Register
destaddr5: DESTADDR
0x1a4 - DMA Channel 0 Destination Address Register
lli5: LLI
0x1a8 - DMA Channel 0 Linked List Item Register
control5: CONTROL
0x1ac - DMA Channel 0 Control Register
config5: CONFIG
0x1b0 - DMA Channel 0 Configuration Register[1]
srcaddr6: SRCADDR
0x1c0 - DMA Channel 0 Source Address Register
destaddr6: DESTADDR
0x1c4 - DMA Channel 0 Destination Address Register
lli6: LLI
0x1c8 - DMA Channel 0 Linked List Item Register
control6: CONTROL
0x1cc - DMA Channel 0 Control Register
config6: CONFIG
0x1d0 - DMA Channel 0 Configuration Register[1]
srcaddr7: SRCADDR
0x1e0 - DMA Channel 0 Source Address Register
destaddr7: DESTADDR
0x1e4 - DMA Channel 0 Destination Address Register
lli7: LLI
0x1e8 - DMA Channel 0 Linked List Item Register
control7: CONTROL
0x1ec - DMA Channel 0 Control Register
config7: CONFIG
0x1f0 - DMA Channel 0 Configuration Register[1]
Auto Trait Implementations
impl Send for RegisterBlock
impl Send for RegisterBlock
impl !Sync for RegisterBlock
impl !Sync for RegisterBlock