Struct lpc177x_8x::gpdma::RegisterBlock[][src]

#[repr(C)]
pub struct RegisterBlock { pub intstat: INTSTAT, pub inttcstat: INTTCSTAT, pub inttcclear: INTTCCLEAR, pub interrstat: INTERRSTAT, pub interrclr: INTERRCLR, pub rawinttcstat: RAWINTTCSTAT, pub rawinterrstat: RAWINTERRSTAT, pub enbldchns: ENBLDCHNS, pub softbreq: SOFTBREQ, pub softsreq: SOFTSREQ, pub softlbreq: SOFTLBREQ, pub softlsreq: SOFTLSREQ, pub dma_config: DMA_CONFIG, pub sync: SYNC, pub srcaddr0: SRCADDR, pub destaddr0: DESTADDR, pub lli0: LLI, pub control0: CONTROL, pub config0: CONFIG, pub srcaddr1: SRCADDR, pub destaddr1: DESTADDR, pub lli1: LLI, pub control1: CONTROL, pub config1: CONFIG, pub srcaddr2: SRCADDR, pub destaddr2: DESTADDR, pub lli2: LLI, pub control2: CONTROL, pub config2: CONFIG, pub srcaddr3: SRCADDR, pub destaddr3: DESTADDR, pub lli3: LLI, pub control3: CONTROL, pub config3: CONFIG, pub srcaddr4: SRCADDR, pub destaddr4: DESTADDR, pub lli4: LLI, pub control4: CONTROL, pub config4: CONFIG, pub srcaddr5: SRCADDR, pub destaddr5: DESTADDR, pub lli5: LLI, pub control5: CONTROL, pub config5: CONFIG, pub srcaddr6: SRCADDR, pub destaddr6: DESTADDR, pub lli6: LLI, pub control6: CONTROL, pub config6: CONFIG, pub srcaddr7: SRCADDR, pub destaddr7: DESTADDR, pub lli7: LLI, pub control7: CONTROL, pub config7: CONFIG, // some fields omitted }

Register block

Fields

0x00 - DMA Interrupt Status Register

0x04 - DMA Interrupt Terminal Count Request Status Register

0x08 - DMA Interrupt Terminal Count Request Clear Register

0x0c - DMA Interrupt Error Status Register

0x10 - DMA Interrupt Error Clear Register

0x14 - DMA Raw Interrupt Terminal Count Status Register

0x18 - DMA Raw Error Interrupt Status Register

0x1c - DMA Enabled Channel Register

0x20 - DMA Software Burst Request Register

0x24 - DMA Software Single Request Register

0x28 - DMA Software Last Burst Request Register

0x2c - DMA Software Last Single Request Register

0x30 - DMA Configuration Register

0x34 - DMA Synchronization Register

0x100 - DMA Channel 0 Source Address Register

0x104 - DMA Channel 0 Destination Address Register

0x108 - DMA Channel 0 Linked List Item Register

0x10c - DMA Channel 0 Control Register

0x110 - DMA Channel 0 Configuration Register[1]

0x120 - DMA Channel 0 Source Address Register

0x124 - DMA Channel 0 Destination Address Register

0x128 - DMA Channel 0 Linked List Item Register

0x12c - DMA Channel 0 Control Register

0x130 - DMA Channel 0 Configuration Register[1]

0x140 - DMA Channel 0 Source Address Register

0x144 - DMA Channel 0 Destination Address Register

0x148 - DMA Channel 0 Linked List Item Register

0x14c - DMA Channel 0 Control Register

0x150 - DMA Channel 0 Configuration Register[1]

0x160 - DMA Channel 0 Source Address Register

0x164 - DMA Channel 0 Destination Address Register

0x168 - DMA Channel 0 Linked List Item Register

0x16c - DMA Channel 0 Control Register

0x170 - DMA Channel 0 Configuration Register[1]

0x180 - DMA Channel 0 Source Address Register

0x184 - DMA Channel 0 Destination Address Register

0x188 - DMA Channel 0 Linked List Item Register

0x18c - DMA Channel 0 Control Register

0x190 - DMA Channel 0 Configuration Register[1]

0x1a0 - DMA Channel 0 Source Address Register

0x1a4 - DMA Channel 0 Destination Address Register

0x1a8 - DMA Channel 0 Linked List Item Register

0x1ac - DMA Channel 0 Control Register

0x1b0 - DMA Channel 0 Configuration Register[1]

0x1c0 - DMA Channel 0 Source Address Register

0x1c4 - DMA Channel 0 Destination Address Register

0x1c8 - DMA Channel 0 Linked List Item Register

0x1cc - DMA Channel 0 Control Register

0x1d0 - DMA Channel 0 Configuration Register[1]

0x1e0 - DMA Channel 0 Source Address Register

0x1e4 - DMA Channel 0 Destination Address Register

0x1e8 - DMA Channel 0 Linked List Item Register

0x1ec - DMA Channel 0 Control Register

0x1f0 - DMA Channel 0 Configuration Register[1]

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