Struct lpc176x_5x::uart0::fcr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn fifoen(&mut self) -> _FIFOENW

Bit 0 - FIFO Enable.

pub fn rxfifores(&mut self) -> _RXFIFORESW

Bit 1 - RX FIFO Reset.

pub fn txfifores(&mut self) -> _TXFIFORESW

Bit 2 - TX FIFO Reset.

pub fn dmamode(&mut self) -> _DMAMODEW

Bit 3 - DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1.

pub fn rxtriglvl(&mut self) -> _RXTRIGLVLW

Bits 6:7 - RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.