Trait libreda_db::netlist::traits::NetlistBase

pub trait NetlistBase: HierarchyBase + NetlistIds {
    // Required methods
    fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId;
    fn pin_direction(&self, pin: &Self::PinId) -> Direction;
    fn pin_name(&self, pin: &Self::PinId) -> Self::NameType;
    fn pin_by_name(
        &self,
        parent_circuit: &Self::CellId,
        name: &str,
    ) -> Option<Self::PinId>;
    fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId;
    fn parent_of_pin_instance(
        &self,
        pin_inst: &Self::PinInstId,
    ) -> Self::CellInstId;
    fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId;
    fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>;
    fn net_of_pin_instance(
        &self,
        pin_instance: &Self::PinInstId,
    ) -> Option<Self::NetId>;
    fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId;
    fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId;
    fn net_by_name(
        &self,
        parent_circuit: &Self::CellId,
        name: &str,
    ) -> Option<Self::NetId>;
    fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>;
    fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)
       where F: FnMut(Self::PinId);
    fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)
       where F: FnMut(Self::PinInstId);
    fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)
       where F: FnMut(Self::NetId);
    fn num_pins(&self, circuit: &Self::CellId) -> usize;
    fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)
       where F: FnMut(Self::PinId);
    fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)
       where F: FnMut(Self::PinInstId);

    // Provided methods
    fn pin_instance(
        &self,
        cell_inst: &Self::CellInstId,
        pin: &Self::PinId,
    ) -> Self::PinInstId { ... }
    fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId> { ... }
    fn each_pin<'a>(
        &'a self,
        circuit: &Self::CellId,
    ) -> Box<dyn Iterator<Item = Self::PinId> + 'a> { ... }
    fn each_pin_instance_vec(
        &self,
        circuit_instance: &Self::CellInstId,
    ) -> Vec<Self::PinInstId> { ... }
    fn each_pin_instance<'a>(
        &'a self,
        circuit_instance: &Self::CellInstId,
    ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a> { ... }
    fn each_external_net<'a>(
        &'a self,
        circuit_instance: &Self::CellInstId,
    ) -> Box<dyn Iterator<Item = Self::NetId> + 'a> { ... }
    fn for_each_external_net<F>(
        &self,
        circuit_instance: &Self::CellInstId,
        f: F,
    )
       where F: FnMut(Self::NetId) { ... }
    fn each_external_net_vec(
        &self,
        circuit_instance: &Self::CellInstId,
    ) -> Vec<Self::NetId> { ... }
    fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId> { ... }
    fn each_internal_net<'a>(
        &'a self,
        circuit: &Self::CellId,
    ) -> Box<dyn Iterator<Item = Self::NetId> + 'a> { ... }
    fn num_internal_nets(&self, circuit: &Self::CellId) -> usize { ... }
    fn num_net_pins(&self, net: &Self::NetId) -> usize { ... }
    fn num_net_pin_instances(&self, net: &Self::NetId) -> usize { ... }
    fn num_net_terminals(&self, net: &Self::NetId) -> usize { ... }
    fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId> { ... }
    fn each_pin_of_net<'a>(
        &'a self,
        net: &Self::NetId,
    ) -> Box<dyn Iterator<Item = Self::PinId> + 'a> { ... }
    fn each_pin_instance_of_net_vec(
        &self,
        net: &Self::NetId,
    ) -> Vec<Self::PinInstId> { ... }
    fn each_pin_instance_of_net<'a>(
        &'a self,
        net: &Self::NetId,
    ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a> { ... }
}

Most basic trait for traversing a netlist. A netlist extends the HierarchyBase and hence is hierarchical. NetlistBase extends the components of the hierarchy with pins and nets. Each cell can have pins. Each cell instance has pin instances that correspond one-to-one to the pins of the template cell. Cells can contain nets. Each pin and each pin instance can be connected to one or zero nets. A net can be connected to an arbitrary number of pins and pin instances.

Pins must have a name and also a signal direction.

Nets can have a name.

Required Methods

fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId

Get the ID of the template pin of this pin instance.

fn pin_direction(&self, pin: &Self::PinId) -> Direction

Get the signal direction of the pin.

fn pin_name(&self, pin: &Self::PinId) -> Self::NameType

Get the name of the pin.

fn pin_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::PinId>

Find a pin by its name. Returns None if no such pin can be found.

fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId

Get the ID of the parent circuit of this pin.

fn parent_of_pin_instance(&self, pin_inst: &Self::PinInstId) -> Self::CellInstId

Get the ID of the circuit instance that holds this pin instance.

fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId

Get the ID of the parent circuit of this net.

fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>

Get the internal net attached to this pin.

fn net_of_pin_instance( &self, pin_instance: &Self::PinInstId, ) -> Option<Self::NetId>

Get the external net attached to this pin instance.

fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId

Get the net of the logical constant zero.

fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId

Get the net of the logical constant one.

fn net_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::NetId>

Find a net by its name inside the parent circuit. Returns None if no such net can be found.

fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>

Get the name of the net.

fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::PinId),

Call a function for each pin of the circuit.

fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)

where F: FnMut(Self::PinInstId),

Call a function for each pin instance of the circuit instance.

fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::NetId),

Call a function for net of the circuit.

fn num_pins(&self, circuit: &Self::CellId) -> usize

Get the number of pins of a circuit.

fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinId),

Call a function for each pin connected to this net.

fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinInstId),

Call a function for each pin instance connected to this net.

Provided Methods

fn pin_instance( &self, cell_inst: &Self::CellInstId, pin: &Self::PinId, ) -> Self::PinInstId

Get the ID of a pin instance given the cell instance and the pin ID.

fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId>

Get a Vec with the IDs of all pins of this circuit.

fn each_pin<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

Iterate over all pins of a circuit.

fn each_pin_instance_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::PinInstId>

Get a Vec with the IDs of all pin instance of this circuit instance.

fn each_pin_instance<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

Iterate over all pin instances of a circuit.

fn each_external_net<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

Iterate over all external nets connected to the circuit instance. A net might appear more than once.

fn for_each_external_net<F>(&self, circuit_instance: &Self::CellInstId, f: F)

where F: FnMut(Self::NetId),

Iterate over all external nets connected to the circuit instance. A net might appear more than once.

fn each_external_net_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::NetId>

Get a vector of all external nets connected to the circuit instance. A net might appear more than once.

fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId>

Get a Vec with all nets in this circuit.

fn each_internal_net<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

Iterate over all defined nets inside a circuit.

fn num_internal_nets(&self, circuit: &Self::CellId) -> usize

Return the number of nets defined inside a cell.

fn num_net_pins(&self, net: &Self::NetId) -> usize

Get the number of pins that are connected to this net.

fn num_net_pin_instances(&self, net: &Self::NetId) -> usize

Get the number of pin instances that are connected to this net.

fn num_net_terminals(&self, net: &Self::NetId) -> usize

Get the number of terminals that are connected to this net.

fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId>

Get a Vec with all pin IDs connected to this net.

fn each_pin_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

Iterate over all pins of a net.

fn each_pin_instance_of_net_vec( &self, net: &Self::NetId, ) -> Vec<Self::PinInstId>

Get a Vec with all pin instance IDs connected to this net.

fn each_pin_instance_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

Iterate over all pins of a net.

Object Safety

This trait is not object safe.

Implementations on Foreign Types

impl<T> NetlistBase for &T

where T: NetlistBase,

fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId

fn each_internal_net<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn num_net_pin_instances(&self, net: &Self::NetId) -> usize

fn each_external_net<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn each_pin_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId>

fn each_pin_instance_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::PinInstId>

fn each_external_net_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::NetId>

fn pin_direction(&self, pin: &Self::PinId) -> Direction

fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)

where F: FnMut(Self::PinInstId),

fn num_internal_nets(&self, circuit: &Self::CellId) -> usize

fn num_pins(&self, circuit: &Self::CellId) -> usize

fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>

fn for_each_external_net<F>(&self, circuit_instance: &Self::CellInstId, f: F)

where F: FnMut(Self::NetId),

fn net_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::NetId>

fn net_of_pin_instance( &self, pin_instance: &Self::PinInstId, ) -> Option<Self::NetId>

fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId>

fn each_pin_instance_of_net_vec( &self, net: &Self::NetId, ) -> Vec<Self::PinInstId>

fn num_net_terminals(&self, net: &Self::NetId) -> usize

fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId

fn pin_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::PinId>

fn pin_instance( &self, cell_inst: &Self::CellInstId, pin: &Self::PinId, ) -> Self::PinInstId

fn each_pin_instance<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::PinId),

fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId

fn each_pin<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinId),

fn each_pin_instance_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn parent_of_pin_instance(&self, pin_inst: &Self::PinInstId) -> Self::CellInstId

fn num_net_pins(&self, net: &Self::NetId) -> usize

fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>

fn pin_name(&self, pin: &Self::PinId) -> Self::NameType

fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::NetId),

fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinInstId),

fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId>

impl<T> NetlistBase for &mut T

where T: NetlistBase,

fn each_pin<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId

fn num_internal_nets(&self, circuit: &Self::CellId) -> usize

fn for_each_external_net<F>(&self, circuit_instance: &Self::CellInstId, f: F)

where F: FnMut(Self::NetId),

fn each_pin_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn pin_direction(&self, pin: &Self::PinId) -> Direction

fn each_pin_instance_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::PinInstId>

fn each_external_net_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::NetId>

fn num_net_pin_instances(&self, net: &Self::NetId) -> usize

fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinId),

fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId>

fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId

fn each_pin_instance<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)

where F: FnMut(Self::PinInstId),

fn num_net_pins(&self, net: &Self::NetId) -> usize

fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinInstId),

fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::NetId),

fn pin_name(&self, pin: &Self::PinId) -> Self::NameType

fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId>

fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId

fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn each_internal_net<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn num_pins(&self, circuit: &Self::CellId) -> usize

fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>

fn each_pin_instance_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>

fn net_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::NetId>

fn each_external_net<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn pin_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::PinId>

fn net_of_pin_instance( &self, pin_instance: &Self::PinInstId, ) -> Option<Self::NetId>

fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId>

fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::PinId),

fn parent_of_pin_instance(&self, pin_inst: &Self::PinInstId) -> Self::CellInstId

fn pin_instance( &self, cell_inst: &Self::CellInstId, pin: &Self::PinId, ) -> Self::PinInstId

fn num_net_terminals(&self, net: &Self::NetId) -> usize

fn each_pin_instance_of_net_vec( &self, net: &Self::NetId, ) -> Vec<Self::PinInstId>

impl<T> NetlistBase for Box<T>

where T: NetlistBase,

fn pin_name(&self, pin: &Self::PinId) -> Self::NameType

fn for_each_external_net<F>(&self, circuit_instance: &Self::CellInstId, f: F)

where F: FnMut(Self::NetId),

fn net_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::NetId>

fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::NetId),

fn each_pin_instance_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::PinInstId>

fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>

fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId

fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId>

fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinId),

fn pin_direction(&self, pin: &Self::PinId) -> Direction

fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)

where F: FnMut(Self::PinInstId),

fn each_pin<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn pin_instance( &self, cell_inst: &Self::CellInstId, pin: &Self::PinId, ) -> Self::PinInstId

fn each_pin_instance_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn parent_of_pin_instance(&self, pin_inst: &Self::PinInstId) -> Self::CellInstId

fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId

fn each_pin_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn num_internal_nets(&self, circuit: &Self::CellId) -> usize

fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId

fn each_pin_instance_of_net_vec( &self, net: &Self::NetId, ) -> Vec<Self::PinInstId>

fn each_pin_instance<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId>

fn net_of_pin_instance( &self, pin_instance: &Self::PinInstId, ) -> Option<Self::NetId>

fn num_pins(&self, circuit: &Self::CellId) -> usize

fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinInstId),

fn num_net_terminals(&self, net: &Self::NetId) -> usize

fn each_internal_net<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn each_external_net_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::NetId>

fn num_net_pins(&self, net: &Self::NetId) -> usize

fn num_net_pin_instances(&self, net: &Self::NetId) -> usize

fn pin_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::PinId>

fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::PinId),

fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId>

fn each_external_net<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>

impl<T> NetlistBase for Rc<T>

where T: NetlistBase,

fn net_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::NetId>

fn each_pin_instance<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn net_of_pin_instance( &self, pin_instance: &Self::PinInstId, ) -> Option<Self::NetId>

fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId

fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId>

fn pin_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::PinId>

fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId

fn parent_of_pin_instance(&self, pin_inst: &Self::PinInstId) -> Self::CellInstId

fn each_pin_instance_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::PinInstId>

fn for_each_external_net<F>(&self, circuit_instance: &Self::CellInstId, f: F)

where F: FnMut(Self::NetId),

fn each_pin_instance_of_net_vec( &self, net: &Self::NetId, ) -> Vec<Self::PinInstId>

fn pin_direction(&self, pin: &Self::PinId) -> Direction

fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinInstId),

fn num_internal_nets(&self, circuit: &Self::CellId) -> usize

fn each_internal_net<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)

where F: FnMut(Self::PinInstId),

fn num_pins(&self, circuit: &Self::CellId) -> usize

fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId

fn pin_instance( &self, cell_inst: &Self::CellInstId, pin: &Self::PinId, ) -> Self::PinInstId

fn num_net_pins(&self, net: &Self::NetId) -> usize

fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>

fn each_pin<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn pin_name(&self, pin: &Self::PinId) -> Self::NameType

fn each_pin_instance_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn num_net_terminals(&self, net: &Self::NetId) -> usize

fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId>

fn each_external_net<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::NetId),

fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinId),

fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::PinId),

fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId>

fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>

fn each_external_net_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::NetId>

fn num_net_pin_instances(&self, net: &Self::NetId) -> usize

fn each_pin_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

impl<T> NetlistBase for Arc<T>

where T: NetlistBase,

fn each_pin_instance_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn net_of_pin_instance( &self, pin_instance: &Self::PinInstId, ) -> Option<Self::NetId>

fn for_each_pin<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::PinId),

fn each_pin_instance_of_net_vec( &self, net: &Self::NetId, ) -> Vec<Self::PinInstId>

fn parent_cell_of_pin(&self, pin: &Self::PinId) -> Self::CellId

fn parent_of_pin_instance(&self, pin_inst: &Self::PinInstId) -> Self::CellInstId

fn pin_instance( &self, cell_inst: &Self::CellInstId, pin: &Self::PinId, ) -> Self::PinInstId

fn each_pin_vec(&self, circuit: &Self::CellId) -> Vec<Self::PinId>

fn for_each_pin_instance_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinInstId),

fn num_pins(&self, circuit: &Self::CellId) -> usize

fn net_name(&self, net: &Self::NetId) -> Option<Self::NameType>

fn each_pin_of_net_vec(&self, net: &Self::NetId) -> Vec<Self::PinId>

fn each_internal_net<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn each_pin_of_net<'a>( &'a self, net: &Self::NetId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn each_pin<'a>( &'a self, circuit: &Self::CellId, ) -> Box<dyn Iterator<Item = Self::PinId> + 'a>

fn pin_direction(&self, pin: &Self::PinId) -> Direction

fn for_each_pin_instance<F>(&self, circuit_inst: &Self::CellInstId, f: F)

where F: FnMut(Self::PinInstId),

fn each_external_net<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::NetId> + 'a>

fn for_each_external_net<F>(&self, circuit_instance: &Self::CellInstId, f: F)

where F: FnMut(Self::NetId),

fn each_external_net_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::NetId>

fn parent_cell_of_net(&self, net: &Self::NetId) -> Self::CellId

fn net_one(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn pin_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::PinId>

fn each_pin_instance_vec( &self, circuit_instance: &Self::CellInstId, ) -> Vec<Self::PinInstId>

fn net_zero(&self, parent_circuit: &Self::CellId) -> Self::NetId

fn each_pin_instance<'a>( &'a self, circuit_instance: &Self::CellInstId, ) -> Box<dyn Iterator<Item = Self::PinInstId> + 'a>

fn for_each_internal_net<F>(&self, circuit: &Self::CellId, f: F)

where F: FnMut(Self::NetId),

fn num_net_pins(&self, net: &Self::NetId) -> usize

fn template_pin(&self, pin_instance: &Self::PinInstId) -> Self::PinId

fn each_internal_net_vec(&self, circuit: &Self::CellId) -> Vec<Self::NetId>

fn num_internal_nets(&self, circuit: &Self::CellId) -> usize

fn num_net_pin_instances(&self, net: &Self::NetId) -> usize

fn num_net_terminals(&self, net: &Self::NetId) -> usize

fn pin_name(&self, pin: &Self::PinId) -> Self::NameType

fn net_of_pin(&self, pin: &Self::PinId) -> Option<Self::NetId>

fn for_each_pin_of_net<F>(&self, net: &Self::NetId, f: F)

where F: FnMut(Self::PinId),

fn net_by_name( &self, parent_circuit: &Self::CellId, name: &str, ) -> Option<Self::NetId>

Implementors

impl NetlistBase for Chip

impl<'b, N, U> NetlistBase for Undo<'b, N, U>

where N: NetlistBase,

impl<N> NetlistBase for RegionSearchAdapter<N>

where N: LayoutBase + NetlistBase, N::Coord: PrimInt + Signed + Debug,

impl<N: NetlistBase> NetlistBase for DBPerf<N>