Module kea_hal::adc[−][src]

Expand description

The ADC Interface

The ADC is disabled at startup and must be enabled (by calling Adc::enable) before any of its registers can be accessed (read or write). Attempts to access these registers will trigger a hardware generated HardFault, which by default resets the microcontroller.

The ADC can be polled for conversion completion with Adc::is_done. Completion will trigger an ADC Interrupt if enabled. See Adc::into_interrupt

Input Modes

The Adc peripheral can operate in either single input or FIFO modes. Single input mode is the mode most commonly thought of when using an ADC. A multiplexer (via Adc::set_channel) is used to connect a single channel to the ADC, and when the conversion is complete the hardware makes the results available in the results register. The software must call Adc::set_channel again to either select a new channel or to restart the conversion on the same channel.

The FIFO mode sets up a hardware buffer of selectable depth (2-8 channels). Once the buffer is filled the Adc peripheral shoves the buffer contents into the multiplexer channel by channel. Likewise, as each conversion is completed the results are buffered into the result register in the same order as the channel select buffer.

Note: FIFO mode is not yet implemented in this HAL

Conversion Modes

The Adc peripheral offers 2 conversion modes, OneShot and Continuous. In OneShot mode, the conversion is started when the channel is selected (or when the channel select buffer is filled in FIFO mode). After completion no new conversion is started until the channel is set again, even if the same channel is used.

In Continuous mode a new conversion is started immediately after the previous one is completed. Changing the channel interrupts the conversion and immediately begins conversion on the new channel (unless the new channel is DummyDisable, then the conversion is allowed to complete, but no new conversion is started). In FIFO mode the input FIFO is reloaded after completion, in other words the same N values are converted on a loop.

Note: Continuous mode is not yet implemented in this HAL

Comparison Mode

Note: Comparison mode is not yet implemented in this HAL

Comparison mode is a hardware feature of the Adc Peripheral. If set, the conversion result is compared to the comparison value. If the result is greater than or less than (depending on configuration) the comparison value the result is moved into the result register. Otherwise, the result is discarded [Note: Unsure if the conversion is restarted in OneShot mode].

A common use case for comparison mode is to enter a low power state with the Adc configured to use the asynchronous clock source and to generate an interrupt on completion. When the input channel crosses the comparison threshold the interrupt is triggered, waking the MCU.

Clocking

The ADC requires a clock signal (ADCK), which is generated from the bus clock, the bus clock divided by 2, the output of the OSC peripheral (OSC_OUT), or an internal asynchronous clock, which, when selected, operates in wait and stop modes. With any of these clock sources a multi-value divider is provided to further divide the incoming clock by 1 (i.e. 1:1), 2, 4, or 8.

The clock frequency must fall within 400kHz to 8MHz (4MHz in low power mode), This is the same for all KEA MCUs. Ideally, the HAL will only present valid options, but that is not yet implemented (pending clocks improvements to output frequencies). For now you are trusted to input the correct frequency.

Note: When using the FIFO mode with FIFO scan mode disabled, the bus clock must be faster than half the ADC clock (ADCK). Bus clock >= ADCK / 2.

Pin Control

This functionality is implemented in the GPIO module. See Analog for details.

Conversion Width

The ADC can be run in 8, 10, or 12 bit modes. These modes are enumerated in AdcResolution.

Hardware Trigger

The ADC conversions can be started by a hardware trigger. This is not implemented in all KEA chips, so implementation here will be Delayed. Use the PAC. Enable is ADC_SC2[ADTRG] = 1, and trigger is the ADHWT source.

Usage

AdcConfig struct

AdcConfig offers public fields to allow for creation in-place. The AdcConfig::calculate_divisor method allows the user to specify the desired Adc Clock frequency (given the clock source frequency). The clock divider which gets the closest to that frequency is chosen.

The AdcConfig structure also implements the Default trait.

let config: AdcConfig = Default::default();

config.calculate_divisor(20_u32.MHz(), 2_u32.MHz());
assert!(matches!(config.clock_divisor, ClockDivisor::_8));