Module kea_hal::system::watchdog [−][src]
Expand description
WDOG - Watchdog Timer
This peripheral runs from an independent timer, and resets the MCU when that timer overflows. Clearing the count value of this timer ensures that software does not leave the cpu stuck in an infinite loop or execute from unknown data.
** NOTE: ** The watchdog does not function well with the debugger active. writing to it is only successful in odd cases, with little effect. Attempting to unlock will trigger a reset. I pulled my hair out over a long weekend before I realized this. Yes, there is a DEBUG mode to set according the KEA64RM. It never works as expected.
Usage
#![no_main] #![no_std] use kea_hal as hal; use cortex_m_rt::entry; use hal::{pac, prelude::*, system}; use panic_halt as _; #[entry] fn main() -> ! { //println!("Hello, world!"); let _cp = cortex_m::Peripherals::take().unwrap(); let dp = pac::Peripherals::take().unwrap(); let watchdog = dp.WDOG.split(); let mut config = watchdog.configuration(); // Reset every 0xBEEF/32kHz seconds. config.period = 0xBEEF; config.clock = system::watchdog::WDogClock::IntRefClock; // Trigger an interrupt before reset to log the error (or something). config.interrupt = true; // load new settings (watchdog will determine if needs to unlock or // not) let watchdog = watchdog.configure(config); // Seal the watchdog so that it cannot be modified until reset let watchdog.into_sealed(); }
Clock Sources
- Bus Clock
- 1kHz Clock
- 32kHz Clock
- Ext Clock
Programmable Timeout Perioid
16 bit timeout value, with optional, fixed, 1/256 prescaler for longer timeout periods.
Servicing the Watchdog.
Call the [Watchdog.service] method to reset the countdown. This is often known as petting the watchdog.
Refresh write sequence: 0x2A6 and then 0x80B4 within 16 bus clocks.
Windowed refresh
Triggers a reset if refresh comes before expected. 16 bit programmable window value. “Provides robust check that program flow is faster than expected”.
Implementer’s Note
This seems useful for asm sequences, but it seems like writing in a high level language would make determining “how soon is too soon” rather difficult.
Watchdog Interrupt
Allows some post-processing to be done after the watchdog triggers, but before the reset. Reset happens 128 bus clocks after the interrupt vector is fetched.
Configuration
Configuration register fields are write-once after reset to prevent accidental modification. These fields can be unlocked for updates by writing 0x20C5 and then 0x28D9 (within 16 bus clocks of each other). Updates must be written within 128 bus clocks after unlocking.
Structs
Disabled | Disabled state |
Enabled | Enabled state |
Locked | Locked state, must unlock before modifying |
Sealed | Locked and sealed state; Device must be reset to unlock. |
Unlocked | Unlocked state, modifiable. |
WDogConfig | Holds watchdog configuration. |
WatchDog | The Watchdog interface presented to the user. |
Enums
WDogClock | Enumeration of watchdog clocks |