Module kea_hal::clocks::ics

Internal Clock Source Peripheral

The ICS peripheral provides clock sources for the MCU. This controls the low-power oscillator and a 1024x multiplying frequency locked loop (FLL). This peripheral is documented in Ch. 20 of KEA64 Sub-family reference manual.

Operational Modes

The ICS has 7 operation modes. These modes determine the source of the clock, if the FLL is bypassed, and if the FLL is turned off for power savings.

FEI - FLL Engaged, Internal Reference Clock Mode

This is the default mode of operation (on reset). This multiplies the asdf 31.25kHz IRC by 1024 (in the FLL) to result in a 16MHz system clock. In order to reach the 40MHz maximum clock speed the sctrim must be stuffed with 0x1FF to yield (approximately) 39.0625kHz IRC clock, which in turn gives a 40MHz system clock in this mode. See Ics::sctrim documentation for me detail.

FEE - FLL Engaged, External Reference mode

This mode is used with external resonators or a clock source. Configuration of the external source is handled in the OSC module. The OSC module must output this signal in the range of 31.25 - 39.0625kHz. Like the FEI mode this will yield a system clock of 32 - 40MHz.

FBI - FLL Bypassed, Interal Reference Clock Mode

This mode bypasses the FLL (but leaves it on, for reasons?) and runs the IRC straight into the output. This would set the system clock between 31.25-39.0625kHz This mode would be used to transition from FBILP mode to FEI mode, in order to allow the FLL output to stabilize (maximum accuracy) before the switch.

FBILP - FLL Disabled, Internal Reference Clock Mode

This mode is just like FBI, but the FLL is turned off to save power. The FLL needs time to stabilized after restarting. If the FLL needs to be used again, for best accuracy ICS should be switched to FBI mode and held there until stabilization, then an alternative timing mode can be used.

FBE - FLL Bypassed, External Reference Mode

This mode is like FBI, except the external reference clock as provided by the OSC module is used instead of the IRC. This mode would be used with a high frequency crystal or clock. This mode would be used to transition from FBELP mode to FEE mode, in order to allow the FLL output to stabilize (maximum accuracy) before the switch.

FBELP - FLL Disabled, External Reference Mode

This mode is to FBE mode as FBILP is to FBI mode. And they said the SAT/ACT was a useless test…

STOP - FLL Disabled? No clock output

This mode is entered whenever the MCU enters the STOP state. ICSIRCLK could be active if enabled (IRCLKEN set) and allowed to work in stop mode (IREFSTEN set).

ICSFFCLK - Fixed Frequency Clock

Only available in the FBE and FBELP modes. ICSFFCLK < ICSOUT/4. Provides the input of the FLL as an output clock source. Passes through RDIV. IREFS must be set to select the IRC.

Definitions

• Core clock - ICSOUTCLK / BDIV - clock for the ARM core (HCLK). 40MHz max
• Platform Clock - ICSOUTCLK / BDIV - clocks crossbar switch and NVIC (FCLK). 40MHz max
• System clock - ICSOUTCLK / BDIV - bus master clock. 40MHz max
• Bus Clock - System clock / BUSDIV - bus slave and peripheral clock. 20MHz Max
• Flash clock - derived from Bus Clock. 20MHz max
• Debug clock - derived from platform clock. 20MHz max
• SWD clock - CMSIS-DAP clock, external, driven by debugger. 20MHz max
• ICSIRCLK - ICS output of the 32kHZ-ish internal reference clock. Can be source for RTC or WDOG modules. 31.25-39.0625kHz
• ICSOUTCLK - output of ICS module’s output MUX, drives core, platform, system clocks and more
• ICSFLLCLK - 1024 * input clock
• ICSFFCLK - input to FLL made available to FTM modules
• OSCCLK - aka OSC_OUT - output of external oscillator (OSC) module. DC-40MHz (bypass), 31.25-39.0625kHz (resonator), 4-20MHz (crystal)
• OSCERCLK - same as OSCCLK, made available to RTC, WDOG, and ADC modules
• LPOCLK - fixed 1kHz output clock, available to RTC or WDOG modules.

Structs

ExtRefClock	External Reference Clock source
FllBypassed	FLL bypassed
FllEnabled	Frequency-Locked Loop (1024x mutliplier) Used
Ics	HAL struct for the Internal clock system.
IntRefClock	Internal Reference Clock source
Interrupt	FLL monitor generates an interrupt when lock is lossed
IrcOut	State of ICSIRCLK (output of the ICS module’s Internal Reference CLocK)
LockStatus	Monitor the frequency-locked loop for loss of lock
LpDisabled	Low Power Mode Disabled
LpEnabled	Low Power Mode Enabled
Poll	FLL monitor must be polled to determine if lock has been lost.
Running	Clock feature is Enabled, but is Disabled on entry to Stop Mode.
Stopped	Clock feature is disabled
SystemClock	struct that represents the state of the System Clock output ICSOUT
Unstoppable	Clock feature is always Enabled, even in Stop mode.

Enums

Error

Custom Error Types

Traits

ICSExt

Grabs ownership of ICS from the PAC.

Type Definitions

DefaultIrcOut

ICSIRCLK defaults to Disabled. Uses Stopped/Running/Unstoppable types