#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCGC5 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `LPTMR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPTMRR {
#[doc = "Access disabled"]
_0,
#[doc = "Access enabled"]
_1,
}
impl LPTMRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LPTMRR::_0 => false,
LPTMRR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LPTMRR {
match value {
false => LPTMRR::_0,
true => LPTMRR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == LPTMRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == LPTMRR::_1
}
}
#[doc = "Possible values of the field `PORTA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PORTAR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PORTAR::_0 => false,
PORTAR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PORTAR {
match value {
false => PORTAR::_0,
true => PORTAR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == PORTAR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == PORTAR::_1
}
}
#[doc = "Possible values of the field `PORTB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PORTBR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PORTBR::_0 => false,
PORTBR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PORTBR {
match value {
false => PORTBR::_0,
true => PORTBR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == PORTBR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == PORTBR::_1
}
}
#[doc = "Possible values of the field `PORTC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PORTCR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PORTCR::_0 => false,
PORTCR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PORTCR {
match value {
false => PORTCR::_0,
true => PORTCR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == PORTCR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == PORTCR::_1
}
}
#[doc = "Possible values of the field `PORTD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PORTDR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PORTDR::_0 => false,
PORTDR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PORTDR {
match value {
false => PORTDR::_0,
true => PORTDR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == PORTDR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == PORTDR::_1
}
}
#[doc = "Possible values of the field `PORTE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PORTER {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PORTER::_0 => false,
PORTER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PORTER {
match value {
false => PORTER::_0,
true => PORTER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == PORTER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == PORTER::_1
}
}
#[doc = "Values that can be written to the field `LPTMR`"]
pub enum LPTMRW {
#[doc = "Access disabled"]
_0,
#[doc = "Access enabled"]
_1,
}
impl LPTMRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LPTMRW::_0 => false,
LPTMRW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LPTMRW<'a> {
w: &'a mut W,
}
impl<'a> _LPTMRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LPTMRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Access disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(LPTMRW::_0)
}
#[doc = "Access enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(LPTMRW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PORTA`"]
pub enum PORTAW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PORTAW::_0 => false,
PORTAW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PORTAW<'a> {
w: &'a mut W,
}
impl<'a> _PORTAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PORTAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PORTAW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PORTAW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PORTB`"]
pub enum PORTBW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTBW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PORTBW::_0 => false,
PORTBW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PORTBW<'a> {
w: &'a mut W,
}
impl<'a> _PORTBW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PORTBW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PORTBW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PORTBW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PORTC`"]
pub enum PORTCW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PORTCW::_0 => false,
PORTCW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PORTCW<'a> {
w: &'a mut W,
}
impl<'a> _PORTCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PORTCW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PORTCW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PORTCW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PORTD`"]
pub enum PORTDW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PORTDW::_0 => false,
PORTDW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PORTDW<'a> {
w: &'a mut W,
}
impl<'a> _PORTDW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PORTDW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PORTDW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PORTDW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PORTE`"]
pub enum PORTEW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl PORTEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PORTEW::_0 => false,
PORTEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PORTEW<'a> {
w: &'a mut W,
}
impl<'a> _PORTEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PORTEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PORTEW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PORTEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Low Power Timer Access Control"]
#[inline]
pub fn lptmr(&self) -> LPTMRR {
LPTMRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Port A Clock Gate Control"]
#[inline]
pub fn porta(&self) -> PORTAR {
PORTAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Port B Clock Gate Control"]
#[inline]
pub fn portb(&self) -> PORTBR {
PORTBR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Port C Clock Gate Control"]
#[inline]
pub fn portc(&self) -> PORTCR {
PORTCR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Port D Clock Gate Control"]
#[inline]
pub fn portd(&self) -> PORTDR {
PORTDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - Port E Clock Gate Control"]
#[inline]
pub fn porte(&self) -> PORTER {
PORTER::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 262530 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Low Power Timer Access Control"]
#[inline]
pub fn lptmr(&mut self) -> _LPTMRW {
_LPTMRW { w: self }
}
#[doc = "Bit 9 - Port A Clock Gate Control"]
#[inline]
pub fn porta(&mut self) -> _PORTAW {
_PORTAW { w: self }
}
#[doc = "Bit 10 - Port B Clock Gate Control"]
#[inline]
pub fn portb(&mut self) -> _PORTBW {
_PORTBW { w: self }
}
#[doc = "Bit 11 - Port C Clock Gate Control"]
#[inline]
pub fn portc(&mut self) -> _PORTCW {
_PORTCW { w: self }
}
#[doc = "Bit 12 - Port D Clock Gate Control"]
#[inline]
pub fn portd(&mut self) -> _PORTDW {
_PORTDW { w: self }
}
#[doc = "Bit 13 - Port E Clock Gate Control"]
#[inline]
pub fn porte(&mut self) -> _PORTEW {
_PORTEW { w: self }
}
}