#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ISFR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ISF0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF0R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF0R::_0 => false,
ISF0R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF0R {
match value {
false => ISF0R::_0,
true => ISF0R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF0R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF0R::_1
}
}
#[doc = "Possible values of the field `ISF1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF1R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF1R::_0 => false,
ISF1R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF1R {
match value {
false => ISF1R::_0,
true => ISF1R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF1R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF1R::_1
}
}
#[doc = "Possible values of the field `ISF2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF2R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF2R::_0 => false,
ISF2R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF2R {
match value {
false => ISF2R::_0,
true => ISF2R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF2R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF2R::_1
}
}
#[doc = "Possible values of the field `ISF3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF3R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF3R::_0 => false,
ISF3R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF3R {
match value {
false => ISF3R::_0,
true => ISF3R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF3R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF3R::_1
}
}
#[doc = "Possible values of the field `ISF4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF4R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF4R::_0 => false,
ISF4R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF4R {
match value {
false => ISF4R::_0,
true => ISF4R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF4R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF4R::_1
}
}
#[doc = "Possible values of the field `ISF5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF5R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF5R::_0 => false,
ISF5R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF5R {
match value {
false => ISF5R::_0,
true => ISF5R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF5R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF5R::_1
}
}
#[doc = "Possible values of the field `ISF6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF6R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF6R::_0 => false,
ISF6R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF6R {
match value {
false => ISF6R::_0,
true => ISF6R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF6R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF6R::_1
}
}
#[doc = "Possible values of the field `ISF7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF7R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF7R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF7R::_0 => false,
ISF7R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF7R {
match value {
false => ISF7R::_0,
true => ISF7R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF7R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF7R::_1
}
}
#[doc = "Possible values of the field `ISF8`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF8R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF8R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF8R::_0 => false,
ISF8R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF8R {
match value {
false => ISF8R::_0,
true => ISF8R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF8R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF8R::_1
}
}
#[doc = "Possible values of the field `ISF9`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF9R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF9R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF9R::_0 => false,
ISF9R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF9R {
match value {
false => ISF9R::_0,
true => ISF9R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF9R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF9R::_1
}
}
#[doc = "Possible values of the field `ISF10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF10R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF10R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF10R::_0 => false,
ISF10R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF10R {
match value {
false => ISF10R::_0,
true => ISF10R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF10R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF10R::_1
}
}
#[doc = "Possible values of the field `ISF11`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF11R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF11R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF11R::_0 => false,
ISF11R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF11R {
match value {
false => ISF11R::_0,
true => ISF11R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF11R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF11R::_1
}
}
#[doc = "Possible values of the field `ISF12`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF12R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF12R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF12R::_0 => false,
ISF12R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF12R {
match value {
false => ISF12R::_0,
true => ISF12R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF12R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF12R::_1
}
}
#[doc = "Possible values of the field `ISF13`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF13R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF13R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF13R::_0 => false,
ISF13R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF13R {
match value {
false => ISF13R::_0,
true => ISF13R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF13R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF13R::_1
}
}
#[doc = "Possible values of the field `ISF14`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF14R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF14R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF14R::_0 => false,
ISF14R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF14R {
match value {
false => ISF14R::_0,
true => ISF14R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF14R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF14R::_1
}
}
#[doc = "Possible values of the field `ISF15`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF15R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF15R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF15R::_0 => false,
ISF15R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF15R {
match value {
false => ISF15R::_0,
true => ISF15R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF15R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF15R::_1
}
}
#[doc = "Possible values of the field `ISF16`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF16R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF16R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF16R::_0 => false,
ISF16R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF16R {
match value {
false => ISF16R::_0,
true => ISF16R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF16R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF16R::_1
}
}
#[doc = "Possible values of the field `ISF17`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF17R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF17R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF17R::_0 => false,
ISF17R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF17R {
match value {
false => ISF17R::_0,
true => ISF17R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF17R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF17R::_1
}
}
#[doc = "Possible values of the field `ISF18`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF18R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF18R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF18R::_0 => false,
ISF18R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF18R {
match value {
false => ISF18R::_0,
true => ISF18R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF18R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF18R::_1
}
}
#[doc = "Possible values of the field `ISF19`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF19R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF19R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF19R::_0 => false,
ISF19R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF19R {
match value {
false => ISF19R::_0,
true => ISF19R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF19R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF19R::_1
}
}
#[doc = "Possible values of the field `ISF20`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF20R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF20R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF20R::_0 => false,
ISF20R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF20R {
match value {
false => ISF20R::_0,
true => ISF20R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF20R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF20R::_1
}
}
#[doc = "Possible values of the field `ISF21`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF21R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF21R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF21R::_0 => false,
ISF21R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF21R {
match value {
false => ISF21R::_0,
true => ISF21R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF21R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF21R::_1
}
}
#[doc = "Possible values of the field `ISF22`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF22R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF22R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF22R::_0 => false,
ISF22R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF22R {
match value {
false => ISF22R::_0,
true => ISF22R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF22R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF22R::_1
}
}
#[doc = "Possible values of the field `ISF23`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF23R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF23R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF23R::_0 => false,
ISF23R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF23R {
match value {
false => ISF23R::_0,
true => ISF23R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF23R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF23R::_1
}
}
#[doc = "Possible values of the field `ISF24`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF24R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF24R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF24R::_0 => false,
ISF24R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF24R {
match value {
false => ISF24R::_0,
true => ISF24R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF24R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF24R::_1
}
}
#[doc = "Possible values of the field `ISF25`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF25R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF25R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF25R::_0 => false,
ISF25R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF25R {
match value {
false => ISF25R::_0,
true => ISF25R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF25R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF25R::_1
}
}
#[doc = "Possible values of the field `ISF26`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF26R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF26R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF26R::_0 => false,
ISF26R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF26R {
match value {
false => ISF26R::_0,
true => ISF26R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF26R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF26R::_1
}
}
#[doc = "Possible values of the field `ISF27`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF27R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF27R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF27R::_0 => false,
ISF27R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF27R {
match value {
false => ISF27R::_0,
true => ISF27R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF27R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF27R::_1
}
}
#[doc = "Possible values of the field `ISF28`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF28R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF28R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF28R::_0 => false,
ISF28R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF28R {
match value {
false => ISF28R::_0,
true => ISF28R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF28R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF28R::_1
}
}
#[doc = "Possible values of the field `ISF29`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF29R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF29R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF29R::_0 => false,
ISF29R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF29R {
match value {
false => ISF29R::_0,
true => ISF29R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF29R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF29R::_1
}
}
#[doc = "Possible values of the field `ISF30`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF30R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF30R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF30R::_0 => false,
ISF30R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF30R {
match value {
false => ISF30R::_0,
true => ISF30R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF30R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF30R::_1
}
}
#[doc = "Possible values of the field `ISF31`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ISF31R {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF31R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ISF31R::_0 => false,
ISF31R::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ISF31R {
match value {
false => ISF31R::_0,
true => ISF31R::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ISF31R::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ISF31R::_1
}
}
#[doc = "Values that can be written to the field `ISF0`"]
pub enum ISF0W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF0W::_0 => false,
ISF0W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF0W<'a> {
w: &'a mut W,
}
impl<'a> _ISF0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF0W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF0W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF1`"]
pub enum ISF1W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF1W::_0 => false,
ISF1W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF1W<'a> {
w: &'a mut W,
}
impl<'a> _ISF1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF1W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF1W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF2`"]
pub enum ISF2W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF2W::_0 => false,
ISF2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF2W<'a> {
w: &'a mut W,
}
impl<'a> _ISF2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF2W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF3`"]
pub enum ISF3W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF3W::_0 => false,
ISF3W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF3W<'a> {
w: &'a mut W,
}
impl<'a> _ISF3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF3W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF3W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF4`"]
pub enum ISF4W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF4W::_0 => false,
ISF4W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF4W<'a> {
w: &'a mut W,
}
impl<'a> _ISF4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF4W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF4W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF4W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF5`"]
pub enum ISF5W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF5W::_0 => false,
ISF5W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF5W<'a> {
w: &'a mut W,
}
impl<'a> _ISF5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF5W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF5W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF5W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF6`"]
pub enum ISF6W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF6W::_0 => false,
ISF6W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF6W<'a> {
w: &'a mut W,
}
impl<'a> _ISF6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF6W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF6W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF7`"]
pub enum ISF7W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF7W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF7W::_0 => false,
ISF7W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF7W<'a> {
w: &'a mut W,
}
impl<'a> _ISF7W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF7W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF7W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF7W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF8`"]
pub enum ISF8W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF8W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF8W::_0 => false,
ISF8W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF8W<'a> {
w: &'a mut W,
}
impl<'a> _ISF8W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF8W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF8W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF8W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF9`"]
pub enum ISF9W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF9W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF9W::_0 => false,
ISF9W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF9W<'a> {
w: &'a mut W,
}
impl<'a> _ISF9W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF9W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF9W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF9W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF10`"]
pub enum ISF10W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF10W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF10W::_0 => false,
ISF10W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF10W<'a> {
w: &'a mut W,
}
impl<'a> _ISF10W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF10W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF10W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF10W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF11`"]
pub enum ISF11W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF11W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF11W::_0 => false,
ISF11W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF11W<'a> {
w: &'a mut W,
}
impl<'a> _ISF11W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF11W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF11W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF11W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF12`"]
pub enum ISF12W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF12W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF12W::_0 => false,
ISF12W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF12W<'a> {
w: &'a mut W,
}
impl<'a> _ISF12W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF12W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF12W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF12W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF13`"]
pub enum ISF13W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF13W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF13W::_0 => false,
ISF13W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF13W<'a> {
w: &'a mut W,
}
impl<'a> _ISF13W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF13W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF13W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF13W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF14`"]
pub enum ISF14W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF14W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF14W::_0 => false,
ISF14W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF14W<'a> {
w: &'a mut W,
}
impl<'a> _ISF14W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF14W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF14W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF14W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF15`"]
pub enum ISF15W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF15W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF15W::_0 => false,
ISF15W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF15W<'a> {
w: &'a mut W,
}
impl<'a> _ISF15W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF15W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF15W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF15W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF16`"]
pub enum ISF16W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF16W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF16W::_0 => false,
ISF16W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF16W<'a> {
w: &'a mut W,
}
impl<'a> _ISF16W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF16W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF16W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF16W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF17`"]
pub enum ISF17W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF17W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF17W::_0 => false,
ISF17W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF17W<'a> {
w: &'a mut W,
}
impl<'a> _ISF17W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF17W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF17W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF17W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF18`"]
pub enum ISF18W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF18W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF18W::_0 => false,
ISF18W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF18W<'a> {
w: &'a mut W,
}
impl<'a> _ISF18W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF18W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF18W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF18W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF19`"]
pub enum ISF19W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF19W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF19W::_0 => false,
ISF19W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF19W<'a> {
w: &'a mut W,
}
impl<'a> _ISF19W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF19W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF19W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF19W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF20`"]
pub enum ISF20W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF20W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF20W::_0 => false,
ISF20W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF20W<'a> {
w: &'a mut W,
}
impl<'a> _ISF20W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF20W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF20W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF20W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF21`"]
pub enum ISF21W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF21W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF21W::_0 => false,
ISF21W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF21W<'a> {
w: &'a mut W,
}
impl<'a> _ISF21W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF21W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF21W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF21W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF22`"]
pub enum ISF22W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF22W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF22W::_0 => false,
ISF22W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF22W<'a> {
w: &'a mut W,
}
impl<'a> _ISF22W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF22W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF22W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF22W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF23`"]
pub enum ISF23W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF23W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF23W::_0 => false,
ISF23W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF23W<'a> {
w: &'a mut W,
}
impl<'a> _ISF23W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF23W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF23W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF23W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF24`"]
pub enum ISF24W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF24W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF24W::_0 => false,
ISF24W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF24W<'a> {
w: &'a mut W,
}
impl<'a> _ISF24W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF24W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF24W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF24W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF25`"]
pub enum ISF25W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF25W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF25W::_0 => false,
ISF25W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF25W<'a> {
w: &'a mut W,
}
impl<'a> _ISF25W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF25W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF25W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF25W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF26`"]
pub enum ISF26W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF26W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF26W::_0 => false,
ISF26W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF26W<'a> {
w: &'a mut W,
}
impl<'a> _ISF26W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF26W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF26W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF26W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF27`"]
pub enum ISF27W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF27W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF27W::_0 => false,
ISF27W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF27W<'a> {
w: &'a mut W,
}
impl<'a> _ISF27W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF27W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF27W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF27W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF28`"]
pub enum ISF28W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF28W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF28W::_0 => false,
ISF28W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF28W<'a> {
w: &'a mut W,
}
impl<'a> _ISF28W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF28W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF28W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF28W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF29`"]
pub enum ISF29W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF29W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF29W::_0 => false,
ISF29W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF29W<'a> {
w: &'a mut W,
}
impl<'a> _ISF29W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF29W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF29W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF29W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF30`"]
pub enum ISF30W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF30W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF30W::_0 => false,
ISF30W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF30W<'a> {
w: &'a mut W,
}
impl<'a> _ISF30W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF30W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF30W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF30W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ISF31`"]
pub enum ISF31W {
#[doc = "Configured interrupt is not detected."]
_0,
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
_1,
}
impl ISF31W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ISF31W::_0 => false,
ISF31W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ISF31W<'a> {
w: &'a mut W,
}
impl<'a> _ISF31W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ISF31W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configured interrupt is not detected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ISF31W::_0)
}
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ISF31W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt Status Flag"]
#[inline]
pub fn isf0(&self) -> ISF0R {
ISF0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Interrupt Status Flag"]
#[inline]
pub fn isf1(&self) -> ISF1R {
ISF1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Interrupt Status Flag"]
#[inline]
pub fn isf2(&self) -> ISF2R {
ISF2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Interrupt Status Flag"]
#[inline]
pub fn isf3(&self) -> ISF3R {
ISF3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Interrupt Status Flag"]
#[inline]
pub fn isf4(&self) -> ISF4R {
ISF4R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Interrupt Status Flag"]
#[inline]
pub fn isf5(&self) -> ISF5R {
ISF5R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Interrupt Status Flag"]
#[inline]
pub fn isf6(&self) -> ISF6R {
ISF6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Interrupt Status Flag"]
#[inline]
pub fn isf7(&self) -> ISF7R {
ISF7R::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Interrupt Status Flag"]
#[inline]
pub fn isf8(&self) -> ISF8R {
ISF8R::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Interrupt Status Flag"]
#[inline]
pub fn isf9(&self) -> ISF9R {
ISF9R::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Interrupt Status Flag"]
#[inline]
pub fn isf10(&self) -> ISF10R {
ISF10R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Interrupt Status Flag"]
#[inline]
pub fn isf11(&self) -> ISF11R {
ISF11R::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Interrupt Status Flag"]
#[inline]
pub fn isf12(&self) -> ISF12R {
ISF12R::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - Interrupt Status Flag"]
#[inline]
pub fn isf13(&self) -> ISF13R {
ISF13R::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Interrupt Status Flag"]
#[inline]
pub fn isf14(&self) -> ISF14R {
ISF14R::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Interrupt Status Flag"]
#[inline]
pub fn isf15(&self) -> ISF15R {
ISF15R::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Interrupt Status Flag"]
#[inline]
pub fn isf16(&self) -> ISF16R {
ISF16R::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Interrupt Status Flag"]
#[inline]
pub fn isf17(&self) -> ISF17R {
ISF17R::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Interrupt Status Flag"]
#[inline]
pub fn isf18(&self) -> ISF18R {
ISF18R::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 19 - Interrupt Status Flag"]
#[inline]
pub fn isf19(&self) -> ISF19R {
ISF19R::_from({
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 20 - Interrupt Status Flag"]
#[inline]
pub fn isf20(&self) -> ISF20R {
ISF20R::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Interrupt Status Flag"]
#[inline]
pub fn isf21(&self) -> ISF21R {
ISF21R::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Interrupt Status Flag"]
#[inline]
pub fn isf22(&self) -> ISF22R {
ISF22R::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Interrupt Status Flag"]
#[inline]
pub fn isf23(&self) -> ISF23R {
ISF23R::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - Interrupt Status Flag"]
#[inline]
pub fn isf24(&self) -> ISF24R {
ISF24R::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Interrupt Status Flag"]
#[inline]
pub fn isf25(&self) -> ISF25R {
ISF25R::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Interrupt Status Flag"]
#[inline]
pub fn isf26(&self) -> ISF26R {
ISF26R::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 27 - Interrupt Status Flag"]
#[inline]
pub fn isf27(&self) -> ISF27R {
ISF27R::_from({
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 28 - Interrupt Status Flag"]
#[inline]
pub fn isf28(&self) -> ISF28R {
ISF28R::_from({
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Interrupt Status Flag"]
#[inline]
pub fn isf29(&self) -> ISF29R {
ISF29R::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Interrupt Status Flag"]
#[inline]
pub fn isf30(&self) -> ISF30R {
ISF30R::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 31 - Interrupt Status Flag"]
#[inline]
pub fn isf31(&self) -> ISF31R {
ISF31R::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt Status Flag"]
#[inline]
pub fn isf0(&mut self) -> _ISF0W {
_ISF0W { w: self }
}
#[doc = "Bit 1 - Interrupt Status Flag"]
#[inline]
pub fn isf1(&mut self) -> _ISF1W {
_ISF1W { w: self }
}
#[doc = "Bit 2 - Interrupt Status Flag"]
#[inline]
pub fn isf2(&mut self) -> _ISF2W {
_ISF2W { w: self }
}
#[doc = "Bit 3 - Interrupt Status Flag"]
#[inline]
pub fn isf3(&mut self) -> _ISF3W {
_ISF3W { w: self }
}
#[doc = "Bit 4 - Interrupt Status Flag"]
#[inline]
pub fn isf4(&mut self) -> _ISF4W {
_ISF4W { w: self }
}
#[doc = "Bit 5 - Interrupt Status Flag"]
#[inline]
pub fn isf5(&mut self) -> _ISF5W {
_ISF5W { w: self }
}
#[doc = "Bit 6 - Interrupt Status Flag"]
#[inline]
pub fn isf6(&mut self) -> _ISF6W {
_ISF6W { w: self }
}
#[doc = "Bit 7 - Interrupt Status Flag"]
#[inline]
pub fn isf7(&mut self) -> _ISF7W {
_ISF7W { w: self }
}
#[doc = "Bit 8 - Interrupt Status Flag"]
#[inline]
pub fn isf8(&mut self) -> _ISF8W {
_ISF8W { w: self }
}
#[doc = "Bit 9 - Interrupt Status Flag"]
#[inline]
pub fn isf9(&mut self) -> _ISF9W {
_ISF9W { w: self }
}
#[doc = "Bit 10 - Interrupt Status Flag"]
#[inline]
pub fn isf10(&mut self) -> _ISF10W {
_ISF10W { w: self }
}
#[doc = "Bit 11 - Interrupt Status Flag"]
#[inline]
pub fn isf11(&mut self) -> _ISF11W {
_ISF11W { w: self }
}
#[doc = "Bit 12 - Interrupt Status Flag"]
#[inline]
pub fn isf12(&mut self) -> _ISF12W {
_ISF12W { w: self }
}
#[doc = "Bit 13 - Interrupt Status Flag"]
#[inline]
pub fn isf13(&mut self) -> _ISF13W {
_ISF13W { w: self }
}
#[doc = "Bit 14 - Interrupt Status Flag"]
#[inline]
pub fn isf14(&mut self) -> _ISF14W {
_ISF14W { w: self }
}
#[doc = "Bit 15 - Interrupt Status Flag"]
#[inline]
pub fn isf15(&mut self) -> _ISF15W {
_ISF15W { w: self }
}
#[doc = "Bit 16 - Interrupt Status Flag"]
#[inline]
pub fn isf16(&mut self) -> _ISF16W {
_ISF16W { w: self }
}
#[doc = "Bit 17 - Interrupt Status Flag"]
#[inline]
pub fn isf17(&mut self) -> _ISF17W {
_ISF17W { w: self }
}
#[doc = "Bit 18 - Interrupt Status Flag"]
#[inline]
pub fn isf18(&mut self) -> _ISF18W {
_ISF18W { w: self }
}
#[doc = "Bit 19 - Interrupt Status Flag"]
#[inline]
pub fn isf19(&mut self) -> _ISF19W {
_ISF19W { w: self }
}
#[doc = "Bit 20 - Interrupt Status Flag"]
#[inline]
pub fn isf20(&mut self) -> _ISF20W {
_ISF20W { w: self }
}
#[doc = "Bit 21 - Interrupt Status Flag"]
#[inline]
pub fn isf21(&mut self) -> _ISF21W {
_ISF21W { w: self }
}
#[doc = "Bit 22 - Interrupt Status Flag"]
#[inline]
pub fn isf22(&mut self) -> _ISF22W {
_ISF22W { w: self }
}
#[doc = "Bit 23 - Interrupt Status Flag"]
#[inline]
pub fn isf23(&mut self) -> _ISF23W {
_ISF23W { w: self }
}
#[doc = "Bit 24 - Interrupt Status Flag"]
#[inline]
pub fn isf24(&mut self) -> _ISF24W {
_ISF24W { w: self }
}
#[doc = "Bit 25 - Interrupt Status Flag"]
#[inline]
pub fn isf25(&mut self) -> _ISF25W {
_ISF25W { w: self }
}
#[doc = "Bit 26 - Interrupt Status Flag"]
#[inline]
pub fn isf26(&mut self) -> _ISF26W {
_ISF26W { w: self }
}
#[doc = "Bit 27 - Interrupt Status Flag"]
#[inline]
pub fn isf27(&mut self) -> _ISF27W {
_ISF27W { w: self }
}
#[doc = "Bit 28 - Interrupt Status Flag"]
#[inline]
pub fn isf28(&mut self) -> _ISF28W {
_ISF28W { w: self }
}
#[doc = "Bit 29 - Interrupt Status Flag"]
#[inline]
pub fn isf29(&mut self) -> _ISF29W {
_ISF29W { w: self }
}
#[doc = "Bit 30 - Interrupt Status Flag"]
#[inline]
pub fn isf30(&mut self) -> _ISF30W {
_ISF30W { w: self }
}
#[doc = "Bit 31 - Interrupt Status Flag"]
#[inline]
pub fn isf31(&mut self) -> _ISF31W {
_ISF31W { w: self }
}
}