[][src]Type Definition k22f::sysmpu::rgdaac::R

type R = R<u32, RGDAAC>;

Reader of register RGDAAC%s

Methods

impl R[src]

pub fn m0um(&self) -> M0UM_R[src]

Bits 0:2 - Bus Master 0 User Mode Access Control

pub fn m0sm(&self) -> M0SM_R[src]

Bits 3:4 - Bus Master 0 Supervisor Mode Access Control

pub fn m0pe(&self) -> M0PE_R[src]

Bit 5 - Bus Master 0 Process Identifier Enable

pub fn m1um(&self) -> M1UM_R[src]

Bits 6:8 - Bus Master 1 User Mode Access Control

pub fn m1sm(&self) -> M1SM_R[src]

Bits 9:10 - Bus Master 1 Supervisor Mode Access Control

pub fn m1pe(&self) -> M1PE_R[src]

Bit 11 - Bus Master 1 Process Identifier Enable

pub fn m2um(&self) -> M2UM_R[src]

Bits 12:14 - Bus Master 2 User Mode Access Control

pub fn m2sm(&self) -> M2SM_R[src]

Bits 15:16 - Bus Master 2 Supervisor Mode Access Control

pub fn m2pe(&self) -> M2PE_R[src]

Bit 17 - Bus Master 2 Process Identifier Enable

pub fn m3um(&self) -> M3UM_R[src]

Bits 18:20 - Bus Master 3 User Mode Access Control

pub fn m3sm(&self) -> M3SM_R[src]

Bits 21:22 - Bus Master 3 Supervisor Mode Access Control

pub fn m3pe(&self) -> M3PE_R[src]

Bit 23 - Bus Master 3 Process Identifier Enable

pub fn m4we(&self) -> M4WE_R[src]

Bit 24 - Bus Master 4 Write Enable

pub fn m4re(&self) -> M4RE_R[src]

Bit 25 - Bus Master 4 Read Enable

pub fn m5we(&self) -> M5WE_R[src]

Bit 26 - Bus Master 5 Write Enable

pub fn m5re(&self) -> M5RE_R[src]

Bit 27 - Bus Master 5 Read Enable

pub fn m6we(&self) -> M6WE_R[src]

Bit 28 - Bus Master 6 Write Enable

pub fn m6re(&self) -> M6RE_R[src]

Bit 29 - Bus Master 6 Read Enable

pub fn m7we(&self) -> M7WE_R[src]

Bit 30 - Bus Master 7 Write Enable

pub fn m7re(&self) -> M7RE_R[src]

Bit 31 - Bus Master 7 Read Enable