[][src]Type Definition k22f::ftm1::synconf::R

type R = R<u32, SYNCONF>;

Reader of register SYNCONF

Methods

impl R[src]

pub fn hwtrigmode(&self) -> HWTRIGMODE_R[src]

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&self) -> CNTINC_R[src]

Bit 2 - CNTIN Register Synchronization

pub fn invc(&self) -> INVC_R[src]

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&self) -> SWOC_R[src]

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&self) -> SYNCMODE_R[src]

Bit 7 - Synchronization Mode

pub fn swrstcnt(&self) -> SWRSTCNT_R[src]

Bit 8 - FTM counter synchronization is activated by the software trigger.

pub fn swwrbuf(&self) -> SWWRBUF_R[src]

Bit 9 - MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

pub fn swom(&self) -> SWOM_R[src]

Bit 10 - Output mask synchronization is activated by the software trigger.

pub fn swinvc(&self) -> SWINVC_R[src]

Bit 11 - Inverting control synchronization is activated by the software trigger.

pub fn swsoc(&self) -> SWSOC_R[src]

Bit 12 - Software output control synchronization is activated by the software trigger.

pub fn hwrstcnt(&self) -> HWRSTCNT_R[src]

Bit 16 - FTM counter synchronization is activated by a hardware trigger.

pub fn hwwrbuf(&self) -> HWWRBUF_R[src]

Bit 17 - MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

pub fn hwom(&self) -> HWOM_R[src]

Bit 18 - Output mask synchronization is activated by a hardware trigger.

pub fn hwinvc(&self) -> HWINVC_R[src]

Bit 19 - Inverting control synchronization is activated by a hardware trigger.

pub fn hwsoc(&self) -> HWSOC_R[src]

Bit 20 - Software output control synchronization is activated by a hardware trigger.