[−][src]Module k210_pac::i2c0
Inter-Integrated Circuit Bus 0
Modules
| clr_activity | Clear ACTIVITY Interrupt Register |
| clr_gen_call | I2C Clear GEN_CALL Interrupt Register |
| clr_intr | Clear Combined and Individual Interrupt Register |
| clr_rd_req | Clear RD_REQ Interrupt Register |
| clr_rx_done | Clear RX_DONE Interrupt Register |
| clr_rx_over | Clear RX_OVER Interrupt Register |
| clr_rx_under | Clear RX_UNDER Interrupt Register |
| clr_start_det | Clear START_DET Interrupt Register |
| clr_stop_det | Clear STOP_DET Interrupt Register |
| clr_tx_abrt | Clear TX_ABRT Interrupt Register |
| clr_tx_over | Clear TX_OVER Interrupt Register |
| comp_param_1 | Component Parameter Register 1 |
| comp_type | Component Type Register |
| comp_version | Component Version Register |
| con | Control Register |
| data_cmd | Data Buffer and Command Register |
| dma_cr | I2C DMA Control Register |
| dma_rdlr | DMA Receive Data Level Register |
| dma_tdlr | DMA Transmit Data Level Register |
| enable | Enable Register |
| enable_status | Enable Status Register |
| fs_spklen | SS, FS or FM+ spike suppression limit |
| general_call | ACK General Call Register |
| intr_mask | Interrupt Mask Register |
| intr_stat | Interrupt Status Register |
| raw_intr_stat | Raw Interrupt Status Register |
| rx_tl | Receive FIFO Threshold Register |
| rxflr | Receive FIFO Level Register |
| sar | Slave Address Register |
| sda_hold | SDA Hold Time Length Register |
| sda_setup | SDA Setup Register |
| ss_scl_hcnt | Standard Speed Clock SCL High Count Register |
| ss_scl_lcnt | Standard Speed Clock SCL Low Count Register |
| status | Status Register |
| tar | Target Address Register |
| tx_abrt_source | Transmit Abort Source Register |
| tx_tl | Transmit FIFO Threshold Register |
| txflr | Transmit FIFO Level Register |
Structs
| RegisterBlock | Register block |
Type Definitions
| CLR_ACTIVITY | Clear ACTIVITY Interrupt Register |
| CLR_GEN_CALL | I2C Clear GEN_CALL Interrupt Register |
| CLR_INTR | Clear Combined and Individual Interrupt Register |
| CLR_RD_REQ | Clear RD_REQ Interrupt Register |
| CLR_RX_DONE | Clear RX_DONE Interrupt Register |
| CLR_RX_OVER | Clear RX_OVER Interrupt Register |
| CLR_RX_UNDER | Clear RX_UNDER Interrupt Register |
| CLR_START_DET | Clear START_DET Interrupt Register |
| CLR_STOP_DET | Clear STOP_DET Interrupt Register |
| CLR_TX_ABRT | Clear TX_ABRT Interrupt Register |
| CLR_TX_OVER | Clear TX_OVER Interrupt Register |
| COMP_PARAM_1 | Component Parameter Register 1 |
| COMP_TYPE | Component Type Register |
| COMP_VERSION | Component Version Register |
| CON | Control Register |
| DATA_CMD | Data Buffer and Command Register |
| DMA_CR | I2C DMA Control Register |
| DMA_RDLR | DMA Receive Data Level Register |
| DMA_TDLR | DMA Transmit Data Level Register |
| ENABLE | Enable Register |
| ENABLE_STATUS | Enable Status Register |
| FS_SPKLEN | SS, FS or FM+ spike suppression limit |
| GENERAL_CALL | ACK General Call Register |
| INTR_MASK | Interrupt Mask Register |
| INTR_STAT | Interrupt Status Register |
| RAW_INTR_STAT | Raw Interrupt Status Register |
| RXFLR | Receive FIFO Level Register |
| RX_TL | Receive FIFO Threshold Register |
| SAR | Slave Address Register |
| SDA_HOLD | SDA Hold Time Length Register |
| SDA_SETUP | SDA Setup Register |
| SS_SCL_HCNT | Standard Speed Clock SCL High Count Register |
| SS_SCL_LCNT | Standard Speed Clock SCL Low Count Register |
| STATUS | Status Register |
| TAR | Target Address Register |
| TXFLR | Transmit FIFO Level Register |
| TX_ABRT_SOURCE | Transmit Abort Source Register |
| TX_TL | Transmit FIFO Threshold Register |